Variable Resistance Memory Device Interconnect Structure
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing manufacturing costs and complexity while achieving high integration densities, particularly in developing next-generation variable resistance memory devices.
Innovation Solution
The design incorporates upper interconnections on a substrate with memory cells and peripheral circuits, featuring conductive contacts that electrically couple word lines and bit lines, allowing for independent connection and isolation, which simplifies the manufacturing process and enhances integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional interconnection structures are used in next-generation memory devices, then manufacturing processes become complex and costly, but integration density requirements cannot be met
Solution Approach 1:
The conductive contacts are divided into unitary members that independently connect word lines and bit lines to upper interconnections. Each conductive contact is a separate, simplified structure rather than a complex integrated network, reducing manufacturing complexity while maintaining high integration density
Solution Approach 2:
The patent transitions from planar interconnections to vertically stacked three-dimensional interconnections. Word lines and bit lines are alternately stacked in the vertical direction, with conductive contacts extending perpendicular to the substrate surface, enabling high integration density without increasing lateral footprint or manufacturing complexity
2Productivity
If more interconnections are added to increase integration density, then device performance improves, but manufacturing cost and process complexity increase
Solution Approach 1:
Multiple conductive contacts are formed as portions of the same conductive material layer, and upper interconnections are formed from the same conductive material. This merging approach allows high integration density with simplified manufacturing processes, reducing the number of separate fabrication steps and material depositions required
Solution Approach 2:
The upper interconnections serve multiple functions: they connect to peripheral circuits, interconnect with conductive contacts, and provide electrical pathways for multiple word lines and bit lines simultaneously. This multi-functionality reduces the total number of separate components needed, lowering manufacturing cost while maintaining high integration density
Data Source
AI summary
A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.