Variable Resistance Memory Leakage Control via Segmented Cell Blocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In variable resistance memory devices with cross point cell array configurations, leakage currents increase with larger memory cell array sizes, degrading reliability and limiting integration density due to current leakage through unselected memory cells, and existing hierarchical bit line structures require additional transistors and occupy more area.
Innovation Solution
Incorporating selection units, such as transistors or diodes, between neighboring cell blocks in the cross point cell array to prevent leakage currents, allowing for effective coupling of neighboring cell blocks and reducing leakage currents without increasing the area occupied by core circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory cell array size is increased to improve integration density, then the degree of integration is improved, but leakage current increases degrading reliability
Solution Approach 1:
The memory cell array is divided into multiple cell blocks (e.g., first cell block, second cell block) that are coupled through selection units. This segmentation allows leakage current to be contained within individual blocks when they are not selected, preventing leakage current from propagating across the entire large array while still achieving high integration density through the expanded memory capacity.
2Reliability
If a hierarchical bit line structure is used to suppress leakage current, then leakage current is reduced, but additional transistors are required increasing device complexity and area
Solution Approach 1:
Selection units are introduced as intermediary components coupled between neighboring cell blocks. These selection units act as mediators that control current flow between blocks, enabling effective leakage current suppression while maintaining a relatively simple overall structure compared to full hierarchical bit line designs.
3Reliability
If a hierarchical bit line structure is used to suppress leakage current, then leakage current is reduced, but the area occupied by core circuits increases
Solution Approach 1:
By segmenting the memory array into multiple cell blocks with selection units at the block level rather than implementing a full hierarchical bit line structure throughout, the design achieves effective leakage current suppression while minimizing the area occupied by core circuits and selection transistors.
Data Source
AI summary
A variable resistance memory device includes a plurality of cell blocks each of which includes a plurality of first lines extending in parallel to each other along a first direction, a plurality of second lines extending in parallel to each other along a second direction crossing the first direction, and a plurality of memory cells including variable resistance layers arranged at intersections of the plurality of first lines and the plurality of second lines and a plurality of selection units coupled to the plurality of first lines and coupling two neighboring cell blocks.