Variable Resistance Memory Device Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in balancing storage capacity and processing speed, with volatile memory devices losing data when power is interrupted and non-volatile devices having inefficiencies in read/write latency and retention characteristics.
Innovation Solution
A variable resistance memory device is developed, comprising a substrate with distinct memory regions, each containing memory cells with different resistance elements and selection elements, where the second memory cells have a lower maximum resistance value than the first, allowing for improved efficiency and performance by combining high storage ability with high processing speed on a single chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single type of memory cell is used across the entire chip, then the manufacturing process is simple, but the chip cannot simultaneously achieve high storage capacity and high processing speed
Solution Approach 1:
The chip is divided into two distinct memory regions: a first memory region with first memory cells having higher resistance elements for high storage capacity, and a second memory region with second memory cells having lower resistance elements for high processing speed. This segmentation allows each region to be optimized for its specific function while maintaining overall chip versatility.
Solution Approach 2:
Different memory cells are designed with different resistance characteristics tailored to their specific functional requirements. The first memory cells use higher resistance elements suitable for storage applications, while the second memory cells use lower resistance elements optimized for processing operations, allowing each local area to have the quality needed for its purpose.
2Manufacturing precision
If different resistance elements are used in different memory regions, then storage capacity and processing speed can be optimized, but height differences between memory cells may affect subsequent photolithography processes
Solution Approach 1:
The patent addresses the height difference issue by transitioning to a three-dimensional stacked memory architecture where multiple memory cells are stacked vertically. This allows the resistance elements to be arranged in different spatial configurations that can accommodate varying resistance requirements while maintaining a compact form factor and reducing planar height differences that would affect photolithography.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The variable resistance memory device enhances chip efficiency by maximizing storage capacity and processing speed, while minimizing height differences between memory cells, thereby improving overall chip performance and securing margins in subsequent photolithography processes.
Implementation Method 1
each of the first memory cells includes a first resistance element and a selection element, each of the second memory cells includes a second resistance element, and a maximum value of a variable resistance of the second resistance element is less than a maximum value of a variable resistance of the first resistance element
Data Source
AI summary
A variable resistance memory device and a method of manufacturing the same, the variable resistance memory device including a substrate including a first memory region and a second memory region; a plurality of first memory cells on the first memory region; and a plurality of second memory cells on the second memory region, wherein each of the first memory cells includes a first resistance element and a selection element, each of the second memory cells includes a second resistance element, and a maximum value of a variable resistance of the second resistance element is less than a maximum value of a variable resistance of the first resistance element.