Variable Resistance Memory Device Spacer Contact Area Reduction
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Solution Overview
Problem
Current variable resistance memory devices, such as PCRAMs, face challenges in reducing the reset current required to switch a phase-change material to an amorphous state, which is influenced by the resistance of the phase-change material layer and the contact area between the lower electrode and the data storage unit.
Innovation Solution
A variable resistance memory device is designed with a multi-layered insulating structure that includes a semiconductor substrate, a lower electrode, spacers, and a variable resistance part with a specific height, where the upper electrode is buried within the hole, reducing the contact area and thereby minimizing the reset current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the contact area between the lower electrode and the data storage unit is reduced, then the reset current is reduced, but the manufacturing precision requirements increase due to the need for precise spacer formation
Solution Approach 1:
The patent divides the spacer formation process into multiple segments: first spacers are formed on the lower electrode, then second spacers are formed on the first spacers, and third spacers are formed on the second spacers. This segmentation allows each spacer layer to be formed with controlled thickness and position, achieving the desired contact area reduction while maintaining manufacturability through standardized deposition and etching processes
Solution Approach 2:
The patent transitions from a two-dimensional contact area problem to a three-dimensional structure by forming vertical spacer layers. The first, second, and third spacers create a multi-level architecture where the contact area is reduced not by shrinking the electrode footprint but by controlling the vertical stacking and lateral offset of spacer layers, adding a dimensional approach to area control
2Area of stationary object
If multiple spacers are formed to define the phase change area, then the contact area is reduced, but the device complexity increases
Solution Approach 1:
The patent implements a nested structure where second spacers are formed on top of first spacers, and third spacers are formed on top of second spacers. Each spacer layer is nested within the vertical profile of the previous layer, creating a compact multi-level structure that defines the phase change area through cumulative lateral offsets rather than requiring laterally dispersed components
Solution Approach 2:
The patent performs preliminary actions by forming sacrificial layers and spacers in advance before depositing the phase change material. The first, second, and third spacers are formed beforehand to pre-define the boundaries of the phase change area, ensuring that the material is deposited only in the desired region and eliminating the need for complex post-deposition patterning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced contact area between the lower electrode and the variable resistance part effectively lowers the reset current, enhancing the performance of the variable resistance memory device.
Implementation Method 1
forming a first spacer on the lower electrode and a sidewall of the hole
Implementation Method 2
forming a third spacer on a lower sidewall of the first spacer below the second spacer by selectively etching the third spacer material
Implementation Method 3
The variable resistance memory devices perform a memory operation to have a set state or a reset state by controlling a phase-change material, which constitutes a data storage unit, to a crystalline state or an amorphous state
Implementation Method 4
Reduction in the reset current of the PCRAMs may be determined by a resistance of the phase-change material layer and a contact area between a lower electrode and the data storage unit
Data Source
AI summary
A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate, a lower electrode formed in a bottom of each of the holes, a first spacer formed on the lower electrode and a sidewall of each of the holes, a second spacer formed on an upper sidewall of the first spacer, a third spacer formed on a lower sidewall of the first spacer below the second spacer, a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole, and an upper electrode formed on the variable resistance part to be buried in each hole.