Variable Resistance Memory Vertical Stacking Integration
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Solution Overview
Problem
Current variable resistance memory technologies face challenges in achieving high integration of memory cell elements and efficient data writing and reading operations while maintaining cost-effectiveness and processing simplicity.
Innovation Solution
The proposed variable resistance memory employs a hierarchical bit line structure with vertically stacked memory cells, utilizing magnetoresistive effect elements and select gate transistors arranged in an oblique direction within the semiconductor substrate, allowing for efficient data writing and reading operations without complex manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory cells are arranged in a conventional planar structure, then manufacturing processes remain simple, but integration density is limited
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to a 3D vertical stacked structure where memory cells are arranged along the vertical direction. This dimensional change enables higher integration density by utilizing the third dimension (vertical stacking) while maintaining compatibility with conventional semiconductor manufacturing processes through standard vertical epitaxial growth and processing techniques
2Ease of operation
If select gate transistors are arranged in the vertical direction, then memory cell access control is improved, but manufacturing complexity increases
Solution Approach 1:
The select gate transistors are arranged vertically along the vertical direction, utilizing the third dimension to achieve improved memory cell access control. This vertical arrangement allows selective activation of memory cells at different vertical levels through word lines, enhancing operational efficiency while the structure remains compatible with conventional vertical processing techniques
Solution Approach 2:
The patent implements selective doping regions (n-type and p-type) at specific locations within the semiconductor substrate to create localized functional regions for source/drain structures and select gate transistors. This local quality differentiation enables precise control of electrical properties in specific areas while maintaining overall manufacturing simplicity through standard selective doping processes
3Quantity of substance
If vertically stacked memory cells are implemented, then storage capacity per unit area increases, but manufacturing precision requirements increase
Solution Approach 1:
The memory cells are stacked vertically to increase storage capacity per unit area by utilizing the vertical dimension. The structure employs standard vertical epitaxial growth and alignment techniques that are already well-established in conventional semiconductor manufacturing, thereby achieving high vertical integration without excessively stringent precision requirements
Solution Approach 2:
The vertically stacked memory cells are divided into multiple independently controllable units, each accessible through selective word lines and bit lines. This segmentation allows precise control and addressing of individual memory cells or groups of cells, reducing the overall precision burden by enabling selective operation rather than requiring simultaneous precise control of all stacked cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high integration of memory cell elements, reduces manufacturing costs, and improves data storage efficiency by allowing for precise control of memory cell access and data states.
Implementation Method 1
utilizing magnetoresistive effect elements
Data Source
AI summary
According to one embodiment, a variable resistance memory includes first and second semiconductor regions in a layer; a memory cell on the first semiconductor region, the memory cell including a first transistor having a first gate connected to a word line and a memory element, the word line extending in a first direction parallel to a surface of the layer; and a second transistor on the second semiconductor region and connected to the memory cell via a bit line, the bit line extending a second direction parallel to the surface of the layer, and the second direction intersecting the first direction. The second semiconductor region extends in a third direction parallel to the surface of the substrate and the third direction intersects the first and second directions.