Variable Resistance Memory Devices With Tapered Conductive Structures
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Solution Overview
Problem
Current variable resistance memory devices face challenges in improving the reliability and operation characteristics, particularly due to suboptimal diode selection elements in cross-point array structures.
Innovation Solution
The proposed solution involves a variable resistance memory device design with conductive structures and diodes where the upper surface of the conductive structures has a width less than the bottom surface of the selection elements, and the use of protrusions to enhance contact, along with a specific stacking of semiconductor patterns and materials for the diodes and variable resistance elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the upper surface width of conductive structures is increased to improve contact area, then contact area increases, but reverse current leakage increases
Solution Approach 1:
The conductive structure is designed with non-uniform width: the upper surface width is smaller than the lower surface width. This local variation in geometry allows the contact area to be sufficient for electrical connection while the narrower upper portion restricts reverse current leakage paths, thus resolving the contradiction between contact area and reverse current leakage.
2Reliability
If protrusions are added to conductive structures to enhance contact, then contact reliability improves, but device complexity increases
Solution Approach 1:
The conductive structure is segmented into multiple protrusions rather than a single continuous structure. These protrusions make contact with different regions of the semiconductor layer, distributing the contact load and improving overall contact reliability while maintaining a relatively simple overall structure that can be integrated into existing device architectures.
Data Source
AI summary
A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.