Variable Resistance Memory Device Tapered Contact Design
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently manufacturing three-dimensional resistance varying type memory devices, such as ReRAM, due to complexities in configuring and integrating variable resistance elements and wiring lines, which affect data storage and retrieval efficiency.
Innovation Solution
The semiconductor memory device employs a cross-point type configuration with intersecting bit lines and word lines, utilizing variable resistance elements like CBRAM, and a specific manufacturing method involving layered structures and tapered contacts to reduce contact resistance and enhance data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If variable resistance elements are integrated with wiring lines in three-dimensional configuration, then data storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory architecture to three-dimensional vertical architecture by stacking multiple variable resistance elements above each other along the vertical direction. This dimensional change enables significantly increased data storage capacity within the same footprint area, allowing multiple storage layers to be integrated vertically rather than horizontally.
Solution Approach 2:
The patent implements a nested structure where multiple variable resistance elements are stacked vertically one above another, with each element containing storage nodes arranged in tiers. The lower elements are positioned beneath upper elements, creating a nested three-dimensional configuration that maximizes space utilization and storage density within a compact volume.
2Reliability
If contact regions are enlarged to reduce contact resistance, then electrical conductivity is improved, but device area is increased
Solution Approach 1:
The patent applies local quality by creating tapered contacts where the contact width varies along the vertical direction. The contacts are narrower at the top and wider at the bottom, concentrating the reduced contact resistance effect at the critical interface regions where current flows between variable resistance elements and wiring lines, while maintaining smaller overall footprint.
Solution Approach 2:
The patent changes the geometric parameter of contact regions by implementing tapered shapes with varying width along the vertical axis. This parameter change allows the contact to provide low resistance at the critical connection points while occupying minimal horizontal space, effectively decoupling contact resistance from device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration and manufacturing method enable efficient data storage and retrieval by minimizing contact resistance and optimizing the area occupied by contact regions, thereby improving the overall performance and capacity of the memory device.
Implementation Method 1
a variable resistance element is employed as a storage element... CBRAM (Conduction Bridge RAM), a storage element utilizing the likes of a chalcogenide compound or metal oxide
Implementation Method 2
a specific manufacturing method involving layered structures and tapered contacts to reduce contact resistance
Data Source
AI summary
According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.