Variable Resistance Memory Device with Unified NOR NAND Controller
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Solution Overview
Problem
The integration of NOR and NAND flash memories in semiconductor memory devices increases manufacturing costs and affects integration density due to the need for separate controllers and address mapping, making it inefficient for storing both frequently updated meta data and less frequently updated user data.
Innovation Solution
A semiconductor memory device with a variable resistance memory cell array divided into NOR and NAND areas, accessed in memory cell units and page units respectively, using a single memory controller and interface to manage access signals, allowing for efficient storage and retrieval of data without the need for separate controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate controllers are used for NOR and NAND flash memories, then random access capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines NOR and NAND flash memory cells into a single memory device with a unified controller. The controller includes a address buffer that can receive and process addresses for both NOR and NAND areas, and a column selection circuit that can select columns from either NOR or NAND memory cells based on the received address. This merging eliminates the need for separate controllers while maintaining random access capability for NOR data and page-based access for NAND data.
2Adaptability or versatility
If separate controllers are used for NOR and NAND flash memories, then access functionality is improved, but manufacturing cost increases
Solution Approach 1:
The unified controller is designed with multi-functional capabilities to handle both NOR and NAND memory access operations. The address buffer can interpret addresses for both memory types, and the column selection circuit can route to either NOR or NAND columns based on address decoding. This universal design provides the versatility of separate controllers while reducing manufacturing costs through integration and elimination of duplicate controller circuits.
3Adaptability or versatility
If separate controllers are used for NOR and NAND flash memories, then access capability is improved, but integration density decreases
Solution Approach 1:
The patent merges NOR and NAND memory cell arrays under a single controller architecture, sharing common control logic, address buffering, and column selection resources. This consolidation reduces the overall area required for controller circuits and improves integration density, while still providing full access capability to both NOR and NAND memory regions through the unified address decoding and column selection mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces manufacturing costs and increases integration density by enabling efficient random access to small data units in NOR areas and bulk data access in NAND areas within a single memory device, optimizing storage capabilities.
Implementation Method 1
the variable resistance material is heated by a temperature higher than its melting temperature (Tm) for a first time period (T1), then quickly quenched into the amorphous state
Implementation Method 2
the variable resistance material is heated by a temperature higher than its crystallization temperature (Tc) but lower than the melting temperature (Tm) for a second time period (T2) longer than T1
Implementation Method 3
The variable resistance material is characterized by two stable states (a crystalline state and an amorphous state), each induced by a particular temperature application. The state of the variable resistance material may be varied according to a current supplied via the bit line BL.
Data Source
AI summary
A semiconductor memory device includes a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.