Variable Resistance Memory Device Vertical Stacking

The patent transitions from a planar two-dimensional layout to a three-dimensional vertical stacking architecture. Memory cell stacks are erected vertically above the substrate, with conductive lines extending in multiple directions (first direction for bit lines, second direction for word lines) and contacts positioned at different vertical levels. This dimensional change enables higher storage density without proportionally increasing the chip footprint, effectively reducing the area required per memory cell while managing interconnection complexity through vertical integration.

The memory device is segmented into multiple independent memory cell stacks, each with its own set of conductive lines and contacts. The bit lines and word lines are divided into multiple segments extending in different directions, with contacts positioned at specific locations to connect to peripheral circuit units. This segmentation allows each stack to be independently optimized and connected, reducing the overall interconnection complexity while maintaining high storage density through compact vertical arrangement.