Variable Resistance Memory Device Pillar Gate Electrode
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Solution Overview
Problem
Current variable resistance memory devices face challenges in achieving high integration density and multi-level cell capabilities due to limitations in switching device structure and current path management.
Innovation Solution
A variable resistance memory device is designed with a pillar-shaped gate electrode, surrounded by bit lines and insulating layers, featuring a variable resistance layer and blocking layers that divert current based on applied voltage, allowing for efficient switching and data storage through depletion layer manipulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar switching devices are used, then device simplicity is maintained, but integration density and multi-level cell capabilities are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) switching devices to a three-dimensional (3D) pillar-shaped gate electrode structure. The gate electrode extends vertically through multiple bit lines and insulating layers, creating a vertical channel that enables multi-level cell operation. This dimensional change allows multiple memory cells to be stacked vertically around a single gate electrode, dramatically increasing integration density without proportionally increasing device footprint.
Solution Approach 2:
The patent implements a nested structure where multiple bit lines and insulating layers are alternately stacked around the central pillar-shaped gate electrode. The variable resistance layer is positioned in the outer portion, surrounding the bit lines. This nested arrangement allows multiple memory cells to share a common gate electrode structure, reducing overall device complexity while achieving high integration density through vertical stacking.
2Productivity
If simple current path management is used, then device operation is straightforward, but multi-level cell capabilities and data storage efficiency are limited
Solution Approach 1:
The patent employs dynamic current path management through voltage-controlled blocking layers. The blocking layers can switch between conductive and insulating states based on applied voltage, dynamically redirecting current flow. When voltage is applied to the pillar-shaped gate electrode, the blocking layers become conductive, allowing current to flow through the variable resistance layer for programming. When no voltage is applied, the blocking layers remain insulating, blocking current flow. This dynamic control enables efficient multi-level cell operation and high data storage efficiency.
Solution Approach 2:
The blocking layers serve as intermediary elements between the bit lines and the variable resistance layer. These layers control current flow by switching between conductive and insulating states, mediating the interaction between the electrical signals applied to the bit lines and the resistance changes in the variable resistance layer. This intermediary function enables precise control of current paths for programming and reading operations in multi-level cell configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high integration density and multi-level cell capabilities by effectively managing current paths and changing resistance levels, enhancing data storage efficiency in semiconductor integrated circuits.
Implementation Method 1
a blocking layer configured to block a path of current flowing through the current transfer layer based on a voltage applied voltage to the pillar-shaped gate electrode, and divert the current flowing through the current transfer layer to the variable resistance layer
Data Source
AI summary
A variable resistance memory device and a driving method thereof are provided. The variable resistance memory device includes a base layer and a pillar-shaped gate electrode formed on the base layer and extending substantially perpendicular to a surface of the base layer. A current transfer layer is formed to surround the pillar-shaped gate electrode. A variable resistance layer formed in an outer portion of the current transfer layer. A blocking layer blocks a path of current flowing through the current transfer layer based on a voltage applied voltage to the pillar-shaped gate electrode, and diverts the current flowing through the current transfer layer to the variable resistance layer.