Variable Thickness Control Gates for NAND Memory Resistance
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Solution Overview
Problem
Conventional three-dimensional NAND memory architectures face challenges in reducing resistance along the channel material, which affects power consumption and operational efficiency due to uniform thickness of control gate and wordline structures.
Innovation Solution
The implementation of vertically-stacked wordlines with control gate structures having a greater vertical thickness than wordlines, allowing a larger proportion of the channel material to be influenced by control gates, thereby reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control gate structures have the same vertical thickness as wordlines, then the structure is simpler to manufacture, but resistance along the channel material increases
Solution Approach 1:
The control gate structures are formed with a greater vertical thickness than the wordline structures in specific regions where they contact the channel material. This local variation in thickness is achieved through selective etching processes that remove portions of the control gate structures not in contact with the channel material, while maintaining the full thickness in contact regions. This resolves the contradiction by improving conductivity where needed without requiring uniform thickness changes throughout the entire structure.
Solution Approach 2:
The patent transitions from a two-dimensional uniform thickness approach to a three-dimensional variable thickness approach for control gate structures. By utilizing the vertical dimension selectively - maintaining full thickness in contact regions with the channel material while reducing thickness in non-contact regions - the invention optimizes electrical conductivity without proportionally increasing manufacturing complexity across the entire structure.
2Reliability
If control gate structures have greater vertical thickness, then a larger proportion of channel material is influenced reducing resistance, but manufacturing precision requirements increase
Solution Approach 1:
The control gate structures are initially formed with a uniform greater vertical thickness before any selective removal. This preliminary formation ensures that all control gate structures have sufficient thickness to influence the channel material effectively. Subsequent selective etching then removes only the excess material in non-contact regions, maintaining the beneficial thickness in contact regions while reducing overall complexity. This preliminary action approach simplifies the precision requirements compared to attempting to form different thicknesses directly.
Solution Approach 2:
The patent introduces sacrificial materials and selective etching processes as intermediary steps to achieve the variable thickness control gate structures. These intermediary processes allow for precise control of the final thickness profile without requiring direct precision control during the primary formation step. The sacrificial materials serve as temporary mediators that guide the selective removal process to achieve the desired thickness variation.
Data Source
AI summary
Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.