Variable Width Semiconductor Interconnects With Self-Aligned Cuts
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Solution Overview
Problem
Conventional self-aligned multiple patterning techniques struggle to achieve variable pitch and line widths for semiconductor interconnects, especially at pitches less than or equal to 38 nm, leading to lithographic variability and potential electrical shorting issues due to misalignment and overheating of partially cut lines.
Innovation Solution
The method involves forming metal lines with variable widths and pitches using spacers that are not subject to lithographic variation, and patterning continuity cuts in signal and power lines that are tolerant of misalignment, ensuring that cuts do not inadvertently extend into neighboring lines or notch them, with notches in power lines limited to 20% or less of their width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SAMP process is used to form interconnect lines, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to inability to achieve variable pitch and line widths at small pitches
Solution Approach 1:
The interconnect formation process is segmented into multiple discrete steps: forming mandrels with first lithography, depositing spacers, forming mandrels with second lithography, and selective removal. This segmentation allows independent optimization of each step, achieving variable pitch and line width control without requiring a single complex lithography process
Solution Approach 2:
The patent transitions from planar lithographic patterning to three-dimensional spacer-based patterning. By depositing conformal spacers on mandrels and using vertical sidewalls as patterning templates, the process achieves sub-lithographic resolution and variable line widths that cannot be obtained through conventional two-dimensional lithography alone
2Productivity
If pitch is reduced to increase interconnect density, then productivity is improved, but reliability deteriorates due to time delayed shorting between lines
Solution Approach 1:
Dielectric material is deposited and cured between the metal lines before final patterning and metallization. This preliminary action ensures that the dielectric barrier is established and stress-relieved before the lines are fully formed, preventing time delayed shorting even when pitch is reduced to increase density
Solution Approach 2:
A dielectric material layer is introduced as an intermediary between adjacent metal lines. This dielectric layer provides electrical isolation and mechanical support, allowing lines to be placed closer together without risking shorting, thus enabling higher interconnect density while maintaining reliability
3Ease of operation
If continuity cuts are lithographically patterned to direct current flow, then ease of operation is improved, but manufacturing precision deteriorates due to overlay misalignment at small pitches
Solution Approach 1:
The continuity cuts are formed through self-aligned processes where the cut locations are determined by the positions of existing structures (mandrels, spacers, or other reference features) rather than by independent lithographic patterning. This self-alignment eliminates overlay errors and ensures precise current flow control even at small pitches where conventional overlay control fails
4Productivity
If spaces between metal lines are reduced to increase density, then productivity is improved, but reliability deteriorates due to dielectric breakdown from electric field stress
Solution Approach 1:
The dielectric material properties are optimized by controlling deposition parameters, cure temperature, and material composition. These parameter changes enhance the dielectric strength and breakdown voltage of the material, allowing smaller spaces between lines to be used without compromising reliability
Solution Approach 2:
The dielectric layer is formed using composite materials or multi-layer dielectric structures that combine materials with complementary properties. This composite approach provides both mechanical support and enhanced electrical insulation, enabling higher line density while preventing dielectric breakdown
Data Source
AI summary
A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines. The line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. The array of metal lines includes a signal line having a continuity cut disposed across its entire line width and a power line adjacent the signal line. The power line has a line width that is greater than twice the minimum line width. The power line has a notch disposed partially across its line width. The notch is aligned with the continuity cut in a direction perpendicular to the longitudinal direction of the metal lines.