Varied Etch-Stop Layout for Epitaxial Source/Drain Scaling
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Solution Overview
Problem
The scaling of multi-gate transistors to smaller dimensions poses overwhelming constraints on semiconductor processes, limiting the possibility of further extending fabrication processes into the 10 nanometer node or sub-10 nanometer node range.
Innovation Solution
The implementation of varied etch-stop layers and epitaxial source or drain structures in integrated circuit fabrication, allowing for modulated nitride etch-stop layer thickness and differentiated backside source or drain contact access features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are scaled to smaller dimensions to increase device density, then the number of functional units per chip area increases, but the constraints on semiconductor fabrication processes become overwhelming and limit extension into 10nm node or sub-10nm node range
Solution Approach 1:
The patent segments the source/drain region fabrication into multiple distinct phases: forming first epitaxial source/drain structures with initial doping, then forming second epitaxial source/drain structures with additional doping in specific regions. This segmentation allows complex doping profiles to be achieved through manageable sequential steps rather than attempting single-step formation, thereby reducing fabrication process complexity while maintaining high device density
Solution Approach 2:
The patent applies local quality by creating differentiated source/drain regions with different doping concentrations and compositions within the same transistor structure. Specifically, lightly-doped extension regions are formed adjacent to the channel, while heavily-doped main source/drain regions are formed in other areas. This localized variation in material properties enables optimized electrical characteristics for different functional requirements, addressing fabrication constraints by allowing precise control over device performance parameters
2Ease of manufacture
If conventional fabrication processes are used to maintain manufacturing simplicity, then ease of manufacture is preserved, but variability in these processes limits extension into 10nm node or sub-10nm node range
Solution Approach 1:
The patent employs preliminary action by pre-forming the first epitaxial source/drain structures with initial doping profiles before subsequent processing steps. These pre-formed structures serve as a foundation that guides later fabrication steps, ensuring consistent alignment and reducing variability. The preliminary doping and structural formation establish a controlled baseline that minimizes process variability in subsequent manufacturing steps, enabling precision at 10nm node while maintaining reasonable manufacturing simplicity
Solution Approach 2:
The patent utilizes parameter changes by systematically varying doping concentrations, epitaxial growth temperatures, and deposition conditions across different fabrication stages. By carefully controlling and adjusting these parameters, the process achieves the required manufacturing precision for 10nm node devices. The method transforms the conventional single-parameter approach into a multi-parameter optimization strategy, where each parameter is tuned to compensate for variability and achieve consistent device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance and yield by optimizing epitaxial source or drain structures and reducing parasitic capacitance, enabling the fabrication of functional components for future technology nodes.
Implementation Method 1
epitaxial source or drain structures
Data Source
AI summary
Integrated circuit structures having varied etch-stop for epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width, and the first epitaxial source or drain structure beneath a first etch-stop layer. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a lateral width greater than the lateral width of the first epitaxial source or drain structure, and the second epitaxial source or drain structure beneath a combination of the first etch stop layer and a second etch-stop layer.