VCDL Gain Calibration Using Sample-and-Hold Delay Measurement
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Solution Overview
Problem
Conventional delay-locked loops face challenges in accurately characterizing the delay time of multiplexers and voltage-controlled delay lines, leading to phase skew accuracy issues and high power consumption, especially when measuring pico-second level delays and dealing with mismatched VCDLs.
Innovation Solution
A pseudo delay-locked loop with a sample and hold portion, phase detector, charge pump, and voltage control delay line, where the controller adjusts the charge pump's current and operating mode to determine the VCDL delay time, and the loop is divided into pre-charge, normal, and sample and hold regions to achieve precise phase alignment with reduced power consumption by spreading current discharge over multiple clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high resolution time domain flash ADC is used to measure delay time difference, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent replaces the conventional time domain flash ADC measurement system with a voltage domain measurement approach. Instead of directly measuring pico-second level time delays using high-power ADCs, the system converts the delay measurement problem into a voltage measurement problem by using the VCDL to convert time delay differences into voltage differences, which can then be measured with lower power consumption while maintaining measurement precision.
Solution Approach 2:
The patent introduces an intermediary measurement approach using a pseudo-DLL system with a sample-and-hold circuit. This intermediary system captures the voltage representing the delay time at a specific phase point, allowing for accurate measurement without requiring high-power continuous operation. The sample-and-hold circuit acts as an intermediary that freezes the voltage state for measurement, reducing the need for continuous high-power ADC operation.
2Measurement precision
If multiple VCDLs are used in parallel structure, then measurement capability is improved, but mismatch between VCDLs degrades measurement performance
Solution Approach 1:
The patent extracts the measurement function from a complex parallel multi-VCDL structure and implements it using a single VCDL within a pseudo-DLL framework. By taking out the measurement capability from the parallel structure, the patent eliminates the mismatch problem inherent in parallel VCDLs while maintaining the ability to measure delay time differences through the single VCDL's voltage output.
Solution Approach 2:
The patent creates a pseudo-DLL that copies the essential delay characteristics of the actual DLL without requiring multiple physical VCDLs. The pseudo-DLL uses a single VCDL to generate a voltage that represents the delay time, effectively copying the measurement function without the hardware overhead and mismatch issues of parallel VCDL structures.
3Speed
If current discharge is concentrated in short period, then phase alignment speed is improved, but electromagnetic interference increases
Solution Approach 1:
The patent implements periodic current discharge through the charge pump circuit that operates in synchronization with the clock signal. Instead of continuous or single-shot current discharge, the charge pump periodically charges and discharges the capacitor in sync with the clock cycles, spreading the current discharge over multiple periods. This periodic action maintains phase alignment capability while reducing peak current magnitude and associated electromagnetic interference.
Solution Approach 2:
The patent segments the current discharge operation into discrete clock-cycle-synchronized steps through the charge pump. Rather than discharging current in a single concentrated pulse, the discharge is segmented into multiple smaller discharge events occurring at different clock cycles, each contributing to the overall phase alignment while individual discharge magnitudes remain lower, thus reducing electromagnetic interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances phase skew accuracy and reduces electromagnetic interference by distributing current over a longer period, allowing for precise phase skew adjustment with minimal power consumption and independent operation from PVT variations.
Implementation Method 1
The VCDL may adjust a delay time from the input clock to the output clock such that the overall delay time is the same as the period of input clock
Implementation Method 2
The CP and LP generally translate the phase error between the input clock and the output clock to a voltage domain
Implementation Method 3
The CP and LP generally translate the phase error between the input clock and the output clock to a voltage domain
Data Source
AI summary
A delay-locked loop includes a phase detector configured to detect a phase difference between a first clock and a second clock, a charge pump configured to increase a charge amount at a capacitive load in accordance with a first charge amount and decrease the charge amount at the capacitive load in accordance with a second charge amount based on a phase difference provided by the phase detector, a sample and hold circuit configured to receive the charge amount from the capacitive load and hold the charge amount, and a voltage control delay line configured to select a delay amount based on the charge amount received from the sample and hold circuit. At least one parameter of the delay-locked loop is configured such that a desired pump current ratio of a delay cell is achieved by adjusting a delay amount of the delay cell and/or an amount of current coupled to the delay cell.