VCSEL Array Current Confinement via Annealed Oxygen Implant
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Solution Overview
Problem
Current semiconductor integrated circuits with VCSEL devices face challenges in integrating high-performance transistors due to the epitaxial layer structure, which limits efficient integration of electronic devices and requires separate circuits for transistors, and lacks efficient current confinement and isolation between VCSEL devices.
Innovation Solution
A semiconductor device with a layer structure including a bottom n-type layer, intermediate p-type layer, n-type modulation doped quantum well structure, spacer layer, and top p-type layer, featuring an annealed oxygen implant region and n-type ion implant region for current confinement and isolation, allowing for integration of electronic circuitry like n-channel HFET devices and p-channel HFET devices within the same chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional epitaxial layer structure is used for VCSEL arrays, then VCSEL device performance is achieved, but integration of high-performance transistors is limited and separate circuits are required
Solution Approach 1:
The patent merges VCSEL device fabrication with transistor device fabrication into a single integrated process. The epitaxial layer structure is designed to include both VCSEL active regions and transistor channel regions, allowing both device types to be formed simultaneously from the same semiconductor substrate through coordinated ion implantation and annealing steps, eliminating the need for separate circuits.
Solution Approach 2:
The epitaxial layer structure serves multiple functions: it provides the active optical region for VCSELs, forms the channel region for transistors, and contains embedded ion implantation regions that serve as both VCSEL contact regions and transistor source/drain regions. This multi-functional design enables high-performance transistors to be integrated directly with VCSEL arrays.
2Reliability
If lateral oxidation is used to form oxide-confined aperture, then current confinement is achieved, but isolation etch between VCSEL devices is necessary
Solution Approach 1:
The patent performs preliminary ion implantation of oxygen into the epitaxial layer at designated locations before VCSEL fabrication. These pre-formed oxygen implantation regions serve as the oxide-confined aperture regions, eliminating the need for subsequent isolation etches between VCSEL devices while maintaining effective current confinement.
Solution Approach 2:
The patent extracts the isolation function from the physical separation process (isolation etch) and embeds it directly into the epitaxial layer structure through oxygen ion implantation. The oxygen implantation regions are formed at the same time as the VCSEL active regions, so no additional isolation steps are needed.
3Ease of operation
If conventional ion implantation is used for current confinement, then current direction control is achieved, but high temperature annealing greater than 800°C is required
Solution Approach 1:
The patent modifies the ion implantation parameters by using oxygen ions at controlled doses and energies, followed by annealing at temperatures greater than 800°C. This parameter optimization allows the oxygen implantation regions to form effective current barriers without requiring excessive temperature that would damage other device structures.
Solution Approach 2:
The patent uses oxygen ions as an intermediary substance that, when implanted and annealed, forms oxide regions that provide current confinement. These oxygen implantation regions act as mediators between the p-type and n-type regions, enabling current direction control through the formation of Schottky barriers at the oxide-semiconductor interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient integration of VCSEL devices with electronic circuitry, providing diode-like current-voltage characteristics, coherent single mode output, and reduced manufacturing costs by eliminating the need for separate transistors and isolation etches, while maintaining high optical power and narrow divergence angle.
Implementation Method 1
The plurality of vertical-cavity surface-emitting laser (VCSEL) devices can have an annealed oxygen implant region that surrounds and extends laterally in a continuous manner between the plurality of VCSEL devices. The annealed oxygen implant region is annealed at a temperature greater than 800°C.
Implementation Method 2
The oxide-confined aperture is typically formed by lateral oxidation or implantation of protons that causes local damage to the epitaxial layer structure.
Implementation Method 3
The n-type modulation doped quantum well structure includes an n-type charge sheet offset from at least one quantum well, and the n-type modulation doped quantum well structure can define respective active optical regions for the plurality of VCSEL devices.
Implementation Method 4
A vertical-cavity surface-emitting laser, or VCSEL, is a type of semiconductor integrated circuit with laser beam emission perpendicular from the top surface
Implementation Method 5
Such a VCSEL array provides for high output power with a single-lobe (spot) output and low divergence angle in the far field
Implementation Method 6
The oxide-confined aperture provides for current confinement and the current confinement region provides for waveguide cladding and optical confinement that supports the vertical propagation mode of light produced by the VCSEL.
Data Source
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AI summary
A semiconductor device includes a plurality of VCSEL devices (or VCSEL device) formed from a layer structure that includes bottom n-type layer(s), intermediate p-type layer(s), an n-type modulation doped quantum well structure formed above the intermediate p-type layer(s), at least one spacer layer formed between the intermediate p-type layer(s) and the n-type modulation doped quantum well structure, and top p-type layer(s). An annealed oxygen implant region is disposed vertically within the at least one spacer layer and an annealed n-type ion implant region is disposed vertically within the top p-type layer(s). Both ion implant regions can surround and extend laterally in a continuous manner between a plurality of VCSEL devices for current funneling and isolation. Furthermore, built-in hole charge Q p for the intermediate p-type layer relative to built-in electron charge Q n for the bottom n-type layer can be configured for diode-like current-voltage characteristics of the VCSEL device(s).