VDMOS Cellular Gate Layout for Higher Breakdown at Intersections
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Solution Overview
Problem
VDMOS devices with cellular structures experience reduced breakdown voltage and increased leakage currents at gate intersections due to non-merging depletion layers, primarily at the diagonals of intersecting gate regions.
Innovation Solution
The VDMOS device incorporates JFET regions and JFET shielding regions with controlled dopant concentrations, separated by separation regions at gate intersections, enhancing depletion layer merging and increasing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ion implantation is applied to form JFET regions under gate regions in a cellular structure, then the switching speed and input impedance are improved, but the breakdown voltage is reduced and leakage currents increase at gate intersections
Solution Approach 1:
The patent applies different dopant concentrations to different regions: higher concentration in JFET regions under non-intersecting gate regions for good switching performance, and lower concentration in JFET shielding regions under gate intersections to prevent breakdown. This local differentiation resolves the contradiction by optimizing each region's properties for its specific function.
Solution Approach 2:
The patent segments the gate regions into two groups with different orientations (first group extending in first direction, second group extending in second direction perpendicular to first direction), creating distinct JFET regions and JFET shielding regions. This segmentation allows independent optimization of doping concentrations in different areas, maintaining switching speed while preventing leakage at intersections.
2Productivity
If gate regions are arranged in a cellular structure with intersections, then the device density and integration are improved, but depletion layers fail to merge at diagonals causing leakage currents
Solution Approach 1:
The patent introduces JFET shielding regions as intermediary elements at gate intersections, positioned between the JFET regions and the substrate. These shielding regions act as mediators that prevent the harmful leakage effect by providing a controlled doping profile that facilitates proper depletion layer behavior at the intersection diagonals.
Solution Approach 2:
The patent applies preliminary anti-action by creating JFET shielding regions with lower dopant concentration before final device operation. This preliminary structure prevents the formation of leakage paths at gate intersections by ensuring proper depletion layer merging, countering the potential harmful effect of the cellular structure's geometric configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves breakdown voltage tolerance and stability by ensuring wider depletion layers at gate intersections, compensating for the negative impact of cellular structure on voltage tolerance.
Implementation Method 1
depletion layers formed by PN junctions at two ends of each of the JFET regions
Implementation Method 2
the VDMOS device fabrication process has a step that forms a junction-gate field-effect transistor JFET region under the gate by applying the ion implantation process
Data Source
AI summary
A VDMOS device and a fabrication method thereof are provided. The device includes unit cells which jointly form a cellular structure. The cellular structure includes spaced-apart source regions and surrounding gate regions. Some gate regions overlap to form gate intersections comprising separation regions; the others form non-intersecting gate regions. Each unit cell has a JFET region corresponding in position to one non-intersecting gate region and a JFET shielding region corresponding in position to one gate intersection. The difference in doping concentrations of different types of dopants in the JFET shielding region surpasses difference in doping concentrations in the JFET regions and therefore depletion layers disposed along diagonals of the gate intersections expand and merge more easily, thereby increasing breakdown voltage along the diagonals. Therefore, the device exhibits enhanced voltage tolerance and stability.