Vector Compare and Store Instruction Index Generation
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Solution Overview
Problem
Existing vector processing methods require additional compute cycles to produce a packed result set from comparison operations, as they output both positive and negative results, increasing processing time and inefficiency.
Innovation Solution
A method utilizing a SIMD processor to compute an index vector, generate memory offsets through a scan operation, and store packed comparison results, leveraging parallel processing to minimize compute cycles and achieve a packed result set efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If vector processors output both positive and negative comparison results in parallel, then processing speed is improved, but the complexity of generating packed result sets increases
Solution Approach 1:
The patent segments the comparison results into two separate vectors: one containing only positive results and another containing only negative results. This segmentation allows the packed result sets to be generated independently for each category, reducing the complexity of managing mixed positive-negative results while maintaining parallel processing speed advantages.
Solution Approach 2:
Instead of filtering positive results from a mixed result set, the patent inverts the approach by separately generating packed result sets for positive and negative outcomes. This inversion simplifies the packing logic by eliminating the need to identify and filter out unwanted results from a combined set.
2Ease of manufacture
If scalar processors are used for comparison operations, then implementation simplicity is maintained, but processing time increases proportionally with data size
Solution Approach 1:
The patent replaces the sequential scalar processing mechanism with a vector processing mechanism that operates on multiple data elements simultaneously. This substitution maintains implementation simplicity through standardized vector instructions while dramatically reducing processing time by leveraging parallel computation capabilities.
3Productivity
If vector processors process large data arrays in parallel, then productivity is improved, but memory access patterns become more complex
Solution Approach 1:
The patent performs preliminary actions by pre-calculating the sizes of positive and negative result sets before generating the packed result sets. This preliminary sizing information is used to allocate appropriate buffer spaces and plan memory access patterns, thereby maintaining high productivity while reducing the complexity of actual memory access operations during result generation.
Data Source
AI summary
The present disclosure is directed to methods to generate a packed result array using parallel vector processing, of an input array and a comparison operation. In one aspect, an additive scan operation can be used to generate memory offsets for each successful comparison operation of the input array and to generate a count of the number of data elements satisfying the comparison operation. In another aspect, the input array can be segmented to allow more efficient processing using the vector registers. In another aspect, a vector processing system is disclosed that is operable to receive a data array, a comparison operation, and threshold criteria, and output a packed array, at a specified memory address, comprising of the data elements satisfying the comparison operation.