Vector Element Compression via Permutation Vectors

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Solution Overview

Problem

Existing vector processing methods require multiple scalar operations to compress selected elements, leading to inefficient use of SIMD operations and unpredictable branches, which hinder processor performance and code generation.

Innovation Solution

A method involving loading criteria and input vectors, generating a comparison vector to identify selected elements, creating a permutation vector to rearrange them, and storing the selected elements in a contiguous manner, allowing for efficient SIMD execution and optimized memory storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If scalar code is used to store selected elements one at a time, then each element can be stored individually, but the number of operations increases and SIMD benefits are negated

Engineering Contradiction:
Improveease of implementationVSAvoidprocessing speed
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent merges multiple scalar store operations into a single vector store operation. By accumulating selected elements in a temporary vector register and then performing one consolidated store operation, the patent eliminates the need for multiple individual scalar stores while maintaining the ability to handle variable numbers of selected elements.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary accumulation of selected elements in a temporary vector register before the final store operation. This preliminary action allows all selected elements to be gathered in advance, enabling a single efficient vector store operation rather than multiple scalar operations during the store phase.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If the number of selected elements is not known in advance, then the operation can handle variable data, but unpredictable branches are created in the loop

Engineering Contradiction:
Improvehandling variable dataVSAvoidprocessor speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the selection and storage process into distinct phases: a selection phase that identifies all selected elements using SIMD comparison operations, and a storage phase that uses a pre-computed permutation vector to place elements in their final positions. This segmentation eliminates the need for unpredictable branches by separating the variable selection logic from the deterministic storage logic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a permutation vector as an intermediary data structure that encodes the positions of all selected elements. This permutation vector acts as a mediator between the selection criteria and the final storage operation, allowing the processor to handle variable numbers of selected elements without creating unpredictable branches, as the permutation vector can be computed deterministically using SIMD operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If multiple scalar operations are used to compress selected elements, then precise control over each element is achieved, but the complexity of the operation increases

Engineering Contradiction:
Improvecontrol precisionVSAvoidoperation complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the operational parameters from scalar to vector level. By using SIMD comparison operations to generate selection masks and permutation vectors, the patent maintains precise control over which elements are selected and where they are stored, but performs these operations on entire vectors simultaneously rather than element-by-element, thereby reducing operational complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9280342B2Vector operations for compressing selected vector elements
Publication Date: 2016.03.08 ORACLE INT CORP
  • US9280342B2 patent drawing
  • US9280342B2 patent drawing
  • US9280342B2 patent drawing

AI summary

A processor, method, and medium for using vector operations to compress selected elements of a vector. An input vector is compared to a criteria vector, and then a subset of the plurality of elements of the input vector are selected based on the comparison. A permutation vector is generated based on the locations of the selected elements and then the permutation vector is used to permute the selected elements of the input vector to an output vector. The selected elements of the input vector are stored in contiguous locations in the leftmost elements of the output vector. Then, the output vector is stored to memory and a pointer to the memory location is incremented by the number of selected elements.