Vector Processing Error Detection via Checker Lane Allocation
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Solution Overview
Problem
High-performance processors in safety-critical applications face challenges in achieving functional safety without significant performance and hardware overhead, as existing error detection methods like lockstep computation require redundant processors, which increase cost and power consumption.
Innovation Solution
Utilizing vector processing circuitry within existing processors to perform checker processing, allowing for error detection by comparing outcomes of main processing with checker processing, thereby reducing the need for redundant hardware and improving performance and error coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lockstep computation with redundant processors is used for error detection, then functional safety and error detection capability are improved, but hardware complexity, device area, and power consumption increase significantly
Solution Approach 1:
The patent merges the error detection function with the existing vector processing circuitry by allocating one or more vector lanes to perform checker processing. Instead of using separate redundant processors, the same vector processing units are utilized to execute both main processing and checker processing, thereby combining multiple functions into a single hardware resource and avoiding additional hardware complexity.
Solution Approach 2:
The vector processing circuitry is designed to be multi-functional, serving both as the main processing unit and as the checker processing unit for error detection. By making the vector lanes universal resources that can be dynamically allocated between main processing and checker processing, the system achieves functional safety without requiring dedicated error detection hardware.
2Reliability
If lockstep computation with redundant processors is used for error detection, then functional safety is improved, but power consumption increases
Solution Approach 1:
The patent combines the error detection function with the existing vector processing circuitry, eliminating the need for separate redundant processors. By reusing the same vector processing units for both main processing and checker processing, the system avoids the additional power consumption that would result from running duplicate processors.
3Device complexity
If vector processing circuitry is used for checker processing, then hardware complexity and power consumption are reduced, but processing performance may be impacted due to resource sharing
Solution Approach 1:
The patent implements periodic switching between main processing and checker processing modes in the vector lanes. During certain time periods, vector lanes are allocated to main processing, while during other periods, they are allocated to checker processing. This periodic time-division multiplexing allows the system to maintain processing performance by ensuring that checker processing does not continuously block main processing resources.
Solution Approach 2:
The allocation of vector lanes between main processing and checker processing is dynamic rather than static. The system can adaptively adjust which vector lanes perform which function based on current processing needs, allowing optimal performance for both main processing and error detection at different times.
Data Source
AI summary
A data processing apparatus (2) has scalar processing circuitry (32-42) and vector processing circuitry (38, 40, 42). When executing main scalar processing on the scalar processing circuitry (32-42), or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (38, 40, 42), checker processing is executed using at least one lane of the plurality of lanes on the vector processing circuitry (38, 40, 42), the checker processing comprising operations corresponding to at least part of the main scalar/vector processing. Errors can then be detected based on a comparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance and reduced hardware cost compared to a dual/triple core lockstep approach.