Vector Friendly Instruction Format for Packed Data Rotation and Halving
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Solution Overview
Problem
Current single instruction multiple data (SIMD) microarchitectures require sequential execution of instructions for multiply-accumulate operations, which can be inefficient for digital signal processing tasks involving packed data elements.
Innovation Solution
The implementation of a vector friendly instruction format that supports packed data elements with rotation and halving capabilities, allowing for concurrent execution of operations through a generic vector friendly instruction format and VEX instruction format, enabling efficient execution of operations like vector signed add with rotation and optional halving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential instruction execution is used for multiply-accumulate operations, then the implementation is simple with existing SIMD microarchitectures, but the processing efficiency is low for digital signal processing tasks
Solution Approach 1:
The patent combines multiple operations (multiply, accumulate, rotation, and halving) into a single instruction format. The vector friendly instruction format allows concurrent execution of these operations through unified circuitry that processes packed data elements in parallel, resolving the contradiction by merging operational complexity into streamlined hardware that achieves high efficiency without proportionally increasing device complexity
Solution Approach 2:
The vector friendly instruction format is designed to support multiple operation types (multiply-accumulate, rotation, halving, and their combinations) through a single universal instruction structure. This multi-functional approach allows the same hardware infrastructure to handle diverse digital signal processing tasks efficiently, improving productivity without requiring separate specialized circuits for each operation
2Loss of time
If multiple instructions are used to perform multiply-accumulate operations, then the operations can be broken down into manageable steps, but the execution time increases due to sequential processing
Solution Approach 1:
The instruction format includes preliminary organization of operations where multiply, accumulate, rotation, and halving are pre-configured as concurrent operations within a single instruction. The circuitry is designed to perform these operations simultaneously on packed data elements, eliminating sequential execution delays and reducing total execution time despite the complexity of coordinating multiple operations
Solution Approach 2:
The patent transitions from sequential one-dimensional instruction execution to concurrent multi-dimensional operation processing. By organizing the instruction format to enable parallel execution across multiple data elements and operation types simultaneously, the system achieves significant time reduction by utilizing the dimension of parallelism rather than processing operations one after another
3Productivity
If concurrent execution of operations is enabled through vector friendly instruction format, then processing efficiency improves, but the instruction format and decoding complexity increases
Solution Approach 1:
The vector friendly instruction format is segmented into distinct field components (operation code fields, data element specification fields, control fields) that map to specific functional units in the execution circuitry. This segmentation allows the complex concurrent operations to be decoded and executed in an organized manner, managing instruction format complexity through structured field division while maintaining high concurrent processing capability
Solution Approach 2:
The patent introduces an intermediary instruction format structure that acts as a mediator between the control unit and the execution circuitry. This format includes specific fields that translate high-level operation requirements into detailed control signals for the concurrent execution units, managing the complexity interface while enabling efficient concurrent processing of multiply, accumulate, rotation, and halving operations
Data Source
AI summary
An apparatus and method for performing addition of signed packed data values using rotation and halving. For example, one embodiment of a processor comprises: a decoder to decode an instruction to generate a decoded instruction, the instruction including an opcode, an immediate, and operands identifying a plurality of packed data source registers and a packed data destination register a first source register to store a first plurality of packed signed words; a second source register to store a second plurality of packed signed words; execution circuitry to execute the decoded instruction, the execution circuitry comprising: adder circuitry to add each packed signed word from the first source register with a selected packed signed word from the second source register to generate a plurality of signed word results, the adder circuitry to select each packed signed word from the second source register in accordance with a rotation value in the immediate of the instruction, the rotation value to indicate an amount of rotation to be applied to the packed signed words in the second source register prior to the adder circuitry performing the adding; and a destination register to store the plurality of signed word results in specified data element locations of the destination register.