Vector Matrix Multiplication Accelerator for Gaussian Elimination
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Solution Overview
Problem
Current methods for solving linear systems of equations, such as Gaussian elimination, face high arithmetic complexity (O(n^3) that becomes cost-prohibitive for systems with millions of equations in applications like network security and large-scale simulations.
Innovation Solution
The use of a vector matrix multiplication accelerator, specifically an analog resistive memory crossbar array, to perform Gaussian elimination operations, reducing arithmetic complexity from O(n^3) to O(n) by executing row operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Gaussian elimination is implemented using traditional sequential processing, then the method is highly reliable and produces accurate results, but the arithmetic complexity of O(n^3) becomes cost prohibitive for systems with millions of equations
Solution Approach 1:
The patent replaces traditional sequential electronic computing with analog resistive memory crossbar arrays that perform matrix operations through physical electrical phenomena. The crossbar array uses Ohm's law and Kirchhoff's laws to naturally compute matrix-vector multiplications in parallel, substituting mechanical/electronic sequential processing with analog physics-based computation.
Solution Approach 2:
The patent transitions from one-dimensional sequential processing to two-dimensional parallel processing by organizing computations across a crossbar array grid. Multiple row operations are performed simultaneously across different rows of the matrix, exploiting the spatial dimension of the crossbar array to achieve parallelism.
2Measurement precision
If traditional digital computing is used for solving large-scale linear systems, then computational precision is maintained, but the computational time and resource requirements become prohibitive
Solution Approach 1:
The patent performs preliminary encoding of the coefficient matrix into the resistive memory crossbar array before the actual computation. The matrix elements are pre-configured as conductance values in the crossbar, allowing the system to directly perform matrix operations without iterative digital computation during the solving phase.
Solution Approach 2:
The patent introduces an analog-to-digital conversion intermediary that bridges the analog crossbar computation and digital processing. The crossbar array performs analog matrix operations, and the results are converted to digital form for further processing, allowing the system to leverage both analog speed and digital precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces computational complexity, enabling faster and more efficient solving of linear systems of equations, particularly for large-scale applications.
Implementation Method 1
delivering, by the controller in at least one multiply operation, an analog voltage corresponding to a non-zero number to a desired row of the augmented coefficient matrix to produce a multiplication result vector
Implementation Method 2
The vector matrix multiplication accelerator performs the three row operations of Gaussian Elimination in a manner that reduces the arithmetic complexity for solving systems of linear equations
Data Source
AI summary
Methods for solving systems of linear equations via utilization of a vector matrix multiplication accelerator are provided. In one aspect, a method includes receiving, from a controller and by the vector matrix multiplication accelerator, an augmented coefficient matrix. The method also comprises implementing Gaussian Elimination using the vector matrix multiplication accelerator by: monitoring, by a register in at least one swap operation, a row order of the augmented coefficient matrix when a first row is swapped with a second row of the augmented coefficient matrix, delivering, by the controller in at least one multiply operation, an analog voltage to a desired row of the augmented coefficient matrix to produce a multiplication result vector, and adding, in at least one add operation, the first row to another desired row of the augmented coefficient matrix to produce an add result vector. Systems and circuits are also provided.