Vector Merge Instruction Hardware Logic for Sorting

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Solution Overview

Problem

Current software algorithms for merging two smaller sorted sets into a larger sorted set require numerous CPU instructions, making the process inefficient and computationally intensive.

Innovation Solution

A hardware implementation within the instruction execution pipeline that uses a single instruction to merge and sort vectors by employing min/max comparison and interleaving logic stages, optimized for various vector sizes, significantly reducing the number of CPU instructions required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software algorithms are used to merge two smaller sorted sets into a larger sorted set, then the merging operation can be performed, but numerous CPU instructions are required making the process inefficient and computationally intensive

Engineering Contradiction:

Improvemerging operation speedVSAvoidCPU instruction cycles

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent replaces the mechanical software-based merging algorithm with a hardware-based vector instruction implementation. The vector merge instruction executes merging operations directly in hardware using specialized execution units, comparison logic, and interleaving circuits, eliminating the need for multiple software CPU instructions and significantly reducing execution time

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The merging operation is divided into distinct hardware implementation stages: comparison stage that identifies minimum and maximum values from corresponding elements of input vectors, and interleaving stage that alternately selects elements from each input vector based on comparison results. This segmentation enables parallel processing and optimizes the merging workflow

Inventive Principle:

Principle #1Segmentation

2Ease of operation

If multiple CPU instructions are used to perform merging operations, then comprehensive control over the merging process is achieved, but the computational complexity and instruction overhead increase

Engineering Contradiction:

Improvemerging process controlVSAvoidnumber of CPU instructions

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The patent combines multiple software instructions into a single hardware vector instruction. The vector merge instruction integrates comparison logic, minimum/max selection, and interleaving operations into one unified hardware execution unit, reducing instruction overhead while maintaining full control over the merging process through a single instruction with appropriate operands

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The vector merge instruction is designed to handle various vector sizes and data types through a universal hardware implementation. The execution unit can process different lengths of input vectors and adapt to various data element sizes, providing comprehensive control flexibility without requiring multiple specialized instructions

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10089075B2Method and apparatus of instruction that merges and sorts smaller sorted vectors into larger sorted vector

Publication Date: 2018.10.02 INTEL CORP

AI summary

A semiconductor chip is described that includes an instruction execution unit having a functional unit, said functional unit having minimum and maximum comparison circuitry followed by interleaving circuitry, said minimum and maximum comparison circuitry to respectively identify minimums and maximums of same positioned elements from two different sets of sorted elements, said interleaving circuitry to interleave said minimums and maximums to help form a third sorted set composed of elements from said different sets and being larger than each of said different sets.