Vector Shuffling Instruction for Lower-Complexity SIMD Execution

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Solution Overview

Problem

Existing vector shuffling operations in SIMD processors require multiple instructions, leading to a complex operation method and reduced execution efficiency.

Innovation Solution

A vector shuffling method and processor design that utilizes a single instruction with a register identifier and shuffling parameter to perform vector shuffling operations, eliminating the need for multiple instructions and reducing system overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple instructions are used to implement vector shuffling operations in existing SIMD processors, then the shuffling operation can be performed, but the operation method becomes complex and execution efficiency is reduced

Engineering Contradiction:
Improveexecution efficiencyVSAvoidoperation method complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines multiple separate instructions into a single unified vector shuffling instruction. The instruction includes a source register identifier, destination register identifier, and shuffling parameter that together define the complete shuffling operation. This merging eliminates the need for multiple instructions and reduces operational complexity while maintaining the shuffling functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal vector shuffling instruction that can perform various shuffling operations through different shuffling parameters. This single instruction format can handle different shuffling patterns (e.g., reverse, rotate, permute) by varying the parameter values, making it multi-functional and eliminating the need for multiple specialized instructions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If multiple instructions are used to implement vector shuffling operations, then the shuffling can be achieved, but system overhead increases

Engineering Contradiction:
Improveexecution efficiencyVSAvoidnumber of instructions
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges multiple instructions into one compact vector shuffling instruction format. This single instruction encapsulates the source register identifier, destination register identifier, and shuffling parameter, reducing the total number of instructions from multiple to one, thereby decreasing system overhead and improving execution efficiency.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If existing shuffle instructions are used, then different shuffling requirements can be met, but multiple instructions are required for specific functions

Engineering Contradiction:
Improveshuffling requirement flexibilityVSAvoidinstruction sequence complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent designs a universal vector shuffling instruction that can accommodate different shuffling requirements through configurable parameters. The shuffling parameter field allows the instruction to adapt to various shuffling patterns (reverse, rotate, permute, etc.) without requiring separate instructions, thus maintaining flexibility while simplifying the instruction sequence.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12405788B2Vector shuffling method, processor and electronic device
Publication Date: 2025.09.02 LOONGSON TECH CORP
  • US12405788B2 patent drawing
  • US12405788B2 patent drawing
  • US12405788B2 patent drawing

AI summary

The present application provides a vector shuffling method, including: receiving an instruction, including: a register identifier and a shuffling parameter; the register identifier includes a source register identifier and a destination register identifier; the source register identifier is used to characterize a source register, which is a register storing a source element that is operated when a vector shuffling operation is performed; the destination register identifier is used to characterize a destination register, which is the register storing a target element that obtained after the vector shuffling operation is performed; and the shuffling parameter is used to indicate a parameter according to which the vector shuffling operation is performed on the source element; executing the instruction to perform the vector shuffling operation on the source element according to the shuffling parameter, and obtaining the target element after performing the vector shuffling operation; writing the target element into the destination register.