Vehicle Control Verification Device for Multi-Core Synchronization
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Solution Overview
Problem
In parallel computer systems, it is challenging to synchronize processes across multiple cores at specific timings, especially when transitioning from single-core to parallelized programs, making it difficult to ensure equivalence and perform thorough testing.
Innovation Solution
A verification device with a timing synchronization unit that acquires synchronization timing information and a control instruction unit that creates control instructions for cores based on this information, ensuring synchronization at designated timings during program execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processes are synchronized only at start points among multiple nodes, then the system can achieve basic process coordination, but it becomes difficult to perform sufficient testing and verify equivalence when parallelized programs are executed
Solution Approach 1:
The verification device generates control instruction information in advance that specifies synchronization timing for multiple cores. The timing synchronization unit determines synchronization timing based on program information before execution, and the control instruction unit creates instructions that guide cores to synchronize at predetermined timings throughout process execution, not just at start points
Solution Approach 2:
The timing synchronization unit determines whether each core has been synchronized at the correct timing based on execution results. This feedback mechanism allows the system to verify synchronization accuracy and adjust control instructions to ensure processes are synchronized at specific timings during parallelized program execution
2Productivity
If a program designed for single core system is parallelized without specific timing control, then the program can be executed on multiple cores, but it becomes difficult to grasp correspondence between processes and ensure equivalence before and after parallelization
Solution Approach 1:
The verification device acts as an intermediary between the parallelized program and the multiple cores. It generates control instruction information that maps processes from the original single-core program to specific synchronization timings for each core, preserving process correspondence information and enabling verification of equivalence between single-core and parallelized execution
Solution Approach 2:
The timing synchronization unit determines synchronization timing in advance based on program information before the parallelized program is executed. This preliminary determination of timing allows the system to maintain process correspondence and verify equivalence by knowing in advance when each core should synchronize its execution
Data Source
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AI summary
The present invention provides a technique capable of synchronizing processes of a plurality of cores so as to correspond a specific timing in a program before being subjected to parallelization when the parallelized program is executed by the plurality of cores. A verification device for a vehicle control device, which has a plurality of cores, includes: a timing synchronization unit that acquires synchronization timing information indicating a timing to synchronize the plurality of cores; and a control instruction unit that creates control instruction information for the plurality of cores based on the synchronization timing information.