Metal Layer Independent Version Identifier Circuit
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Solution Overview
Problem
The existing methods for changing the version identifier of semiconductor chips are costly and complex, particularly when the change is not related to functional changes in the metal layer that generates the identifier, and they violate IEEE standards when using e-fuses for encoding.
Innovation Solution
A versioning system that allows the chip version identifier to be changed from any metal layer using selector circuitry and gate circuitry, which generates status bits based on input values from multiple layers, reducing the need for additional changes to the metal layer and avoiding the use of e-fuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the version identifier is generated on a metal layer that is not affected by functional changes, then the version identifier remains stable, but an additional change to the metal layer is necessary incurring additional mask charge
Solution Approach 1:
The version identifier generation is segmented from the functional metal layers. A dedicated version identifier generation circuit is implemented on a separate metal layer (typically the last metal layer), allowing independent version identification from functional changes. This segmentation eliminates the need to modify functional layers for version updates, reducing mask charge costs while maintaining version stability.
Solution Approach 2:
An intermediary version identifier generation circuit is introduced between the functional logic and the version identification process. This intermediary circuit reads status bits that reflect functional changes without requiring direct modification of the functional metal layers, thereby maintaining version stability while avoiding additional manufacturing costs.
2Adaptability or versatility
If e-fuses are used to encode the version identifier, then the version identifier can be changed, but IEEE standards are violated and fuse read operation is required before boundary scan
Solution Approach 1:
The mechanical e-fuse system is replaced with a logic-based version identifier generation circuit. Instead of using physical fuse breaks to encode version information, the invention uses logical operations on status bits to generate the version identifier. This substitution eliminates IEEE standard violations and removes the requirement for fuse read operations before boundary scan, while maintaining version changeability.
Solution Approach 2:
Instead of directly modifying the version identifier through e-fuses, the invention creates a logical copy of version information through status bits and generation circuitry. The version identifier is generated by copying and processing status bit information through logical operations, avoiding direct physical modification and IEEE standard conflicts.
3Adaptability or versatility
If the version identifier is changed by modifying a metal layer, then the version identifier is updated, but other metal layers must also be altered increasing complexity
Solution Approach 1:
The version identifier generation is segmented into a dedicated circuit on a specific metal layer, isolated from functional metal layers. This allows version updates to be implemented by modifying only the version identifier generation circuit without affecting other metal layers, reducing overall device complexity while maintaining update capability.
Solution Approach 2:
The version identifier generation function is extracted from the functional metal layers and placed on a separate dedicated circuit. This extraction allows independent modification of the version identifier without requiring changes to other metal layers, simplifying the overall device structure while preserving version update flexibility.
Data Source
AI summary
Version circuitry for use with a semiconductor chip having multiple layers includes multiple status bits. The versioning circuitry includes, for each status bit, gate circuitry, first selector circuitry in a first layer, and second selector circuitry in a second layer. The gate circuitry generates a value for the status bit based at least on a first input and a second input. The first selector circuitry is coupled to the gate circuitry and is configured to select a value for the first input. The second selector circuitry is coupled to the gate circuitry and is configured to select a value for the second input. The gate circuitry generates a default value for the status bit when the first input and the second input each have a default value and generates an opposite value for the status bit when either the first input or the second input has an opposite value.