Vertical 1S1R RRAM Layout for High-Density Cross-Point Arrays
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Solution Overview
Problem
Existing RRAM devices face limitations in achieving high integration density due to the additional area required for transistors and the horizontal extension of conductors, which restricts the formation of high-density cross-point arrays.
Innovation Solution
The RRAM bit cells are formed as a 1S1R configuration with selector devices coupled in series, allowing for integration in a vertical direction using word lines and horizontal bit lines, forming strips that extend along different planes, thereby increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 1T1R configuration is used, then transistor functionality is achieved, but additional area is required reducing integration density
Solution Approach 1:
The patent extracts the transistor from the bit cell configuration and replaces it with a selector device, removing the problematic element that consumed excessive area while maintaining the necessary switching functionality for reliable operation
Solution Approach 2:
The patent changes the device configuration parameter from 1T1R to 1S1R, fundamentally altering the bit cell structure to use a selector device instead of a transistor, which enables higher integration density while preserving functionality
2Ease of manufacture
If conductors extend horizontally, then routing is simplified, but integration density is limited
Solution Approach 1:
The patent introduces vertical stacking of bit cells in the third dimension, allowing word lines and bit lines to extend in different planes and intersect in three-dimensional space, thereby increasing integration density without complicating the horizontal routing layout
3Ease of manufacture
If selector devices are formed in-plane, then fabrication is simplified, but cross-point array formation is limited
Solution Approach 1:
The patent forms selector devices that extend vertically between different horizontal planes, enabling word lines and bit lines to intersect at multiple points in three-dimensional space, which facilitates high-density cross-point array formation while maintaining fabrication compatibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a significant increase in integration density by allowing RRAM bit cells to be horizontally formed in a plane with vertical word lines and horizontal bit lines, surpassing the limitations of traditional 1T1R configurations.
Implementation Method 1
RRAM devices, which exhibit a switching behavior between a high resistance state (HRS) and a low resistance state (LRS)
Data Source
AI summary
A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.