Vertical 1T-1R Memory Cells for ReRAM Bit Density
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Solution Overview
Problem
ReRAM memory arrays face challenges in size and bit density due to sneak paths and leakage currents, which affect the ability to efficiently write, erase, and read data, especially in cross-point arrays and 1T-1R configurations.
Innovation Solution
The implementation of vertical 1T-1R memory cells with a vertically-oriented pillar-shaped transistor coupled in series with a resistivity-switching element, where the transistor has a controlling electrode connected to a word line and terminals connected to a bit line, allowing for effective current limiting and increased bit density by interdigitating memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a cross-point array of ReRAM devices is used, then the area is minimized (4F2), but sneak paths make sensing difficult and the array size is severely limited
Solution Approach 1:
A vertical transistor is introduced as an intermediary element between the ReRAM device and the bit line. This transistor acts as a mediator that enables reliable bit sensing by controlling current flow through the ReRAM device, while maintaining the compact cross-point array structure. The transistor's gate is controlled by the word line, allowing selective activation of memory cells without requiring additional select lines.
2Reliability
If a diode is used as selecting element in series with each ReRAM device, then larger arrays are possible, but leakage current must be very low and current limiting is ineffective
Solution Approach 1:
The patent changes the key parameter of the selecting element from a diode to a vertical transistor, which provides superior control over current flow. The transistor can dynamically adjust its resistance based on gate voltage, enabling effective current limiting during write operations and reducing leakage currents. This parameter change allows for lower leakage currents compared to diode-based selections.
3Loss of energy
If a horizontal transistor is used in 1T-1R configuration, then current limiting is effective, but the cell footprint increases to 6F2
Solution Approach 1:
The patent transitions from a horizontal transistor layout to a vertical transistor architecture. By standing the transistor upright with its channel extending vertically, the device achieves effective current limiting while reducing the lateral footprint. The vertical orientation allows the transistor to share space more efficiently with the ReRAM device, achieving a compact cell structure that maintains current control capabilities.
4Reliability
If more unselected bits are reverse biased during write operation, then sneak paths are suppressed, but write current must overcome higher leakage currents reducing speed
Solution Approach 1:
The vertical transistor serves as an intermediary that provides precise control over current flow to the ReRAM device. During write operations, the transistor can be fully turned on for selected cells, providing a low-resistance path that overwhelms any leakage currents from unselected cells. This mediator approach allows aggressive reverse biasing of unselected bits for sneak path suppression while maintaining high write speeds through the selected cell's transistor-controlled current path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances bit density by allowing for multi-level operation and reduced leakage currents, enabling efficient writing, erasing, and reading of data while minimizing sneak paths, thereby improving the overall performance of ReRAM memory arrays.
Implementation Method 1
Upon application of sufficient voltage, current, or other stimulus, the reversible resistivity-switching material switches to a stable low-resistance state. This resistivity-switching is reversible, such that subsequent application of an appropriate voltage, current, or other stimulus can return the reversible resistivity-switching material to a stable high-resistance state.
Data Source
AI summary
Vertical 1T-1R memory cells, memory arrays of vertical 1T-1R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor and a resistivity-switching element coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode coupled to a word line that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor includes a first terminal coupled to a bit line, a second terminal comprising the controlling electrode coupled to a word line, and a third terminal coupled to the resistivity-switching element.