Vertical 1T0C Memory Structure for Dense Capacitorless Charge Storage
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Solution Overview
Problem
The existing DRAM technology faces challenges in reducing the size of memory units due to leakage currents and the need for capacitor structures, which limits storage performance and integration density.
Innovation Solution
The implementation of a memory structure with transistors and storage layers where conductive channels extend perpendicular to the substrate, allowing storage layers to store and transfer electric charges between them, eliminating the need for capacitors and reducing the size of each storage unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor structures are used in DRAM units, then storage function is achieved, but unit size increases and integration density decreases
Solution Approach 1:
The patent extracts and removes the capacitor component from the traditional 1T1C DRAM structure, creating a capacitorless memory architecture where charge is stored directly in the channel region of the transistor rather than in a separate capacitor structure
Solution Approach 2:
The patent merges the storage function into the transistor structure itself by forming the storage region within the channel, combining what were previously separate components (transistor and capacitor) into an integrated 1T0C structure
2Reliability
If conventional DRAM structures are used, then storage capability is provided, but leakage current affects stability
Solution Approach 1:
The patent transitions from planar charge storage to three-dimensional charge storage by forming vertical channel structures and utilizing the depth dimension of the transistor channel as the storage region, enabling better charge confinement and reduced leakage
Solution Approach 2:
The patent applies different material compositions and doping profiles at different locations within the channel structure to optimize charge storage in specific regions while minimizing leakage paths, creating localized properties that enhance reliability
3Quantity of substance
If more substrate area is used, then manufacturing is easier, but integration density decreases
Solution Approach 1:
The patent utilizes vertical channel structures that extend in the depth direction of the substrate, enabling multiple storage units to be stacked or arranged in three-dimensional configurations rather than requiring proportional increases in planar substrate area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a 1T0C storage unit structure, reducing the size and increasing integration density, while improving storage efficiency and stability by eliminating the need for capacitors and optimizing substrate area usage.
Implementation Method 1
The storage layers are configured to store electric charges and transfer the electric charges between the storage layers and the conductive channels interconnected therewith
Data Source
AI summary
A memory and a method for manufacturing the same are provided. The memory includes a substrate; at least one pair of transistors on a surface of the substrate, in which conductive channels of the transistors extend in a direction perpendicular to the surface of the substrate; storage layers, which each are located, in the direction perpendicular to the surface of the substrate, on a side surface of each of the transistors, the storage layers are interconnected with the conductive channels of the transistors, any one of the storage layers is located between the pair of transistors, and the storage layers are configured to store electric charges and transfer the electric charges between the storage layers and the conductive channels interconnected therewith.