Vertical 1T1R Memory Structure for High-Density Embedded Cells
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Solution Overview
Problem
Conventional embedded memory designs are limited by large area requirements due to the inclusion of access transistors, leading to reduced efficiency, increased costs, and reliability issues from etching processes.
Innovation Solution
A vertically stacked access transistor design with a smaller profile is implemented, using a pillar structure for the channel material, allowing for a denser layout and reduced unit cell dimension from 25F² to 4F², and incorporating a variable resistance memory layer between source lines and dielectric layers to minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If access transistors are included in embedded memory design, then leakage current is limited and program disturb errors are prohibited, but area requirements increase and efficiency decreases
Solution Approach 1:
The patent transitions from a planar transistor layout to a vertical stacked configuration. The access transistor is formed vertically above the memory element, with the channel extending in the vertical direction rather than horizontally. This dimensional change allows the transistor to occupy significantly less planar area while maintaining its function of controlling current flow to prevent leakage and program disturb errors.
Solution Approach 2:
The access transistor structure is nested vertically above the memory element. The channel material pillar is positioned directly over the memory element, with the gate electrode surrounding the channel in a stacked configuration. This nesting arrangement integrates the transistor and memory element in a compact vertical stack, reducing the overall footprint while preserving the transistor's protective function.
2Ease of manufacture
If conventional etching processes are used for memory device fabrication, then manufacturing is achieved, but surface damage and reliability issues occur
Solution Approach 1:
The patent replaces conventional mechanical etching processes with a direct deposition approach. Instead of etching trenches and filling them with conductive materials, the word lines are formed by directly depositing conductive layers in the desired patterns. This substitution eliminates the mechanical stress and surface damage associated with etching while achieving the same interconnect functionality.
3Area of stationary object
If vertically stacked access transistor design is implemented, then area is reduced and density is enhanced, but manufacturing complexity increases
Solution Approach 1:
The vertically stacked transistor is segmented into distinct functional layers: the channel material pillar, gate electrode, source/drain regions, and insulating layers. Each segment is formed through separate deposition and patterning steps, allowing for precise control of each component's properties while simplifying the overall manufacturing process compared to attempting to form the entire vertical structure in a single step.
Data Source
AI summary
Some embodiments relate to an embedded memory device with vertically stacked source, drain and gate connections. The semiconductor memory device includes a substrate and a pillar of channel material extending in a first direction. A bit line is disposed over the pillar of channel material and is coupled to the pillar of channel material, and extends in a second direction that is perpendicular to the first direction. Word lines are on opposite sides of the pillar of channel material and extend in a third direction. The third direction is perpendicular to the second direction. A dielectric layer separates the word lines from the pillar of channel material. Source lines extend in the third direction over the substrate, directly beneath the word lines. Variable resistance memory layers are between the source lines and an outer sidewall of the dielectric layer, laterally surrounding the sidewalls of the pillar of channel material.