Vertical 2D Semiconductor Transistor for High-Density Integration
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Solution Overview
Problem
Current semiconductor technologies face challenges in densely integrating transistors and semiconductor devices due to limitations in vertical configurations, particularly in utilizing 2D semiconductors effectively for enhanced electrical properties.
Innovation Solution
The development of vertical type transistors and semiconductor devices that incorporate a 2D semiconductor channel layer, with specific configurations including source/drain electrode layers, gate electrodes, and insulating films, allowing for efficient electrical connectivity and isolation, and utilizing materials like MoS2, MoSe2, and WSe2, to achieve improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If horizontal transistors are used, then 2D semiconductors can be applied with good electrical properties, but integration density is limited
Solution Approach 1:
The patent transitions from horizontal transistor configuration to vertical configuration, changing the spatial dimension of the channel from in-plane to out-of-plane. The channel layer extends vertically between source and drain electrodes stacked in the third direction, enabling better utilization of 2D semiconductor materials while achieving higher integration density through vertical stacking of multiple transistor layers
2Productivity
If vertical type transistors are used, then integration density is improved, but effective utilization of 2D semiconductors is challenging
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions of the vertical transistor. The channel layer uses 2D semiconductor materials with specific crystalline orientations, while source/drain regions use differently doped semiconductor materials. The gate insulating film and spacer layers have distinct dielectric properties, creating locally optimized regions that collectively achieve both high integration density and excellent electrical performance
3Productivity
If multiple electrode layers are stacked vertically, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the transistor structure into distinct functional segments: first and second source/drain electrode layers, channel layer, gate insulating film, and spacer layers. Each segment performs a specific function and can be independently optimized and manufactured. This segmentation allows complex vertical structures to be built through modular deposition and etching processes, reducing overall manufacturing complexity
Data Source
AI summary
A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.