Vertical Anti-Fuse Structure for FinFET Programming Margin
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Solution Overview
Problem
The reliability and operation margin of traditional anti-fuses in semiconductor ICs are compromised as they scale down, particularly in FinFET and gate-all-around devices, due to the thinning of gate oxide layers and process changes affecting their performance.
Innovation Solution
A new anti-fuse structure with a breakdown path from a source/drain contact via to a source/drain electrode separated by an insulator, where the insulator is thicker than typical gate oxide layers, allowing for a higher programming voltage and more reliable operation, utilizing epitaxially-grown and heavily-doped semiconductor materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional anti-fuse structures with thin gate oxide layers are used, then device size can be reduced, but reliability and operation margin deteriorate
Solution Approach 1:
The patent transitions from a planar breakdown path (gate to channel/drain) to a vertical breakdown path (source/drain contact via through insulator to source/drain electrode). This dimensional change allows the use of thicker insulator layers while maintaining compact device footprint, thereby improving reliability without increasing device size.
Solution Approach 2:
The patent introduces an intermediary insulator layer (such as silicon oxide or silicon nitride) with thickness of 50-200 nm between the source/drain contact via and source/drain electrode. This intermediary layer provides a controlled breakdown path that enhances operation margin and reliability compared to direct gate oxide breakdown, while still enabling miniaturization.
2Manufacturing precision
If thicker insulator layers are used in the breakdown path, then programming voltage margin improves, but device area increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking the insulator layer between the source/drain contact via and source/drain electrode in the vertical direction. This allows thick insulator layers (50-200 nm) to be accommodated without increasing lateral device area, as the breakdown path extends vertically rather than laterally.
Solution Approach 2:
The insulator layer is nested within the existing source/drain contact structure, utilizing the vertical space above the source/drain electrode. This nesting approach allows the thick insulator to be integrated without adding lateral dimensions, maintaining compact device area while providing sufficient programming voltage margin.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This new anti-fuse structure provides enhanced reliability and programming margin by allowing a larger programming voltage and improved resistance change detection, suitable for integration into existing IC manufacturing flows.
Implementation Method 1
a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down
Data Source
AI summary
A fuse structure includes first and second transistors where each of the first and the second transistors has a source terminal, a drain terminal, and a gate terminal; a first source/drain contact disposed on the source terminal of the first transistor; a second source/drain contact disposed on the drain terminal of the second transistor; an insulator disposed laterally between the first and the second source/drain contacts; a source/drain contact via disposed on the first source/drain contact; and a program line connected to the source/drain contact via, wherein a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down.