Vertical BiFET Isolation via High-Resistivity Interlayer

Solution Overview

Problem

Conventional BiFET semiconductor devices with laterally integrated FETs and HBTs face challenges in achieving effective isolation, limiting their performance and flexibility, especially when trying to adopt more advanced PHEMT structures, which are possible with vertical integration but are difficult to achieve due to the need for precise isolation of vertically stacked components.

Innovation Solution

A BiFET semiconductor device is designed with a high-resistivity structure between the HBT and FET, comprising multiple layers grown sequentially on a semi-insulating substrate, including low-temperature grown GaAs or InGaP layers doped with oxygen or transition metals, and high-purity layers to prevent impurity influence, enabling effective isolation and improved performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If lateral integration of FETs and HBTs is used, then manufacturing is easier, but isolation between devices is insufficient and performance is limited

Engineering Contradiction:

Improveisolation effectivenessVSAvoidvertical structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from lateral integration to vertical integration, stacking the HBT and FET structures vertically on the same substrate. This dimensional change enables better isolation between devices while maintaining compact footprint, directly addressing the isolation effectiveness issue in conventional lateral integration approaches

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces an intermediate layer structure between the vertically stacked HBT and FET components. This intermediate layer acts as a mediator that provides electrical isolation and prevents interference between the two device types, enabling effective isolation in the vertical configuration

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If vertical integration is attempted, then advanced PHEMT structures can be adopted, but effective isolation of vertically stacked components is very difficult

Engineering Contradiction:

ImprovePHEMT structure adoptionVSAvoidisolation between stacked components

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces an intermediate layer structure between the vertically stacked HBT and FET components. This intermediate layer acts as a mediator that provides electrical isolation and prevents interference between the two device types, enabling effective isolation in the vertical configuration

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies different material compositions and doping levels in specific regions of the vertical structure, particularly in the intermediate isolation layers. This local quality variation optimizes isolation effectiveness in critical regions while maintaining device performance, enabling reliable vertical integration with PHEMT structures

Inventive Principle:

Principle #3Local quality

3Ease of manufacture

If laterally integrated BiFETs are used, then manufacturing is simpler, but FET performance is limited compared to PHEMT

Engineering Contradiction:

Improvelateral integration simplicityVSAvoidFET performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent transitions from lateral integration to vertical integration, stacking the HBT and FET structures vertically on the same substrate. This dimensional change enables better isolation between devices while maintaining compact footprint, directly addressing the isolation effectiveness issue in conventional lateral integration approaches

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent modifies material parameters including doping concentrations, layer thicknesses, and material compositions in the vertical structure. These parameter changes enable the fabrication of PHEMT-like structures with superior electron mobility and performance compared to conventional lateral MESFETs

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution allows for the successful vertical integration of FETs and HBTs, enhancing the BiFET device's performance and flexibility, enabling the use of more advanced PHEMT structures and broader application in RF and mobile communication devices.

Implementation Method 1

a first layer on top of the HBT structure's emitter contact layer to provide the required high resistivity

Methodology Applied

Scientific EffectElectrical resistivity: Electrical Resistance

Implementation Method 2

a second layer which is a high purity layer on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure

Methodology Applied

Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS7385236B2BiFET semiconductor device having vertically integrated FET and HBT

Publication Date: 2008.06.10 VISUAL PHOTONICS EPITAXY

AI summary

The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bottom to top on a semi-insulating substrate. The high-resistivity structure comprises at least two layers. A first layer is on top of the HBT structure to provide the required high resistivity, while the second layer having a high purity is on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure.