Vertical Bipolar and MOS Transistor Integration via Selective Epitaxy
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Solution Overview
Problem
Conventional methods face challenges in simultaneously forming complementary MOS transistors and vertical bipolar transistors with a common base within the constraints of conventional CMOS technology, requiring a method that is both simple and compatible with existing processes.
Innovation Solution
A method involving the formation of semiconductor layers, selective epitaxy, and doping processes to create vertical bipolar transistors and MOS transistors, where insulating regions and gate structures are used to delimit and separate the transistors, allowing for the integration of both types on a semiconductor substrate while maintaining compatibility with CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to form MOS transistors and vertical bipolar transistors separately in different portions of the chip, then each transistor type can be formed with established processes, but the manufacturing process becomes complex and incompatible with conventional CMOS technology
Solution Approach 1:
The patent merges the formation of MOS transistors and vertical bipolar transistors into a single integrated process flow. By using the same semiconductor layer, insulating layer, and processing steps for both transistor types, the method enables simultaneous formation in the same chip portion while maintaining compatibility with conventional CMOS technology, thereby simplifying the manufacturing process.
Solution Approach 2:
The patent creates universal structures that serve dual functions: the same semiconductor layer and insulating layer configurations form both MOS transistors and vertical bipolar transistors. The common base structure and shared processing steps provide multi-functionality, allowing a single process to manufacture both transistor types without requiring separate dedicated process lines.
2Productivity
If vertical bipolar transistors with common base are integrated into CMOS technology, then high-density memory integration is enabled, but leakage currents become a significant issue
Solution Approach 1:
The patent extracts and eliminates leakage current paths by implementing precise insulating structures. Insulating layers and regions are strategically positioned to separate the common base from surrounding structures, removing harmful leakage paths while preserving the high-density integration benefits of the vertical bipolar transistor configuration.
Solution Approach 2:
The patent introduces insulating layers and regions as intermediary elements between the bipolar transistor components and surrounding structures. These intermediary insulating structures act as barriers that block leakage currents while allowing the high-density memory integration to function effectively, thus mediating between the conflicting requirements of density and leakage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the simultaneous and efficient formation of vertically integrated bipolar transistors and MOS transistors with a common base, effectively addressing the challenge of leakage currents and enabling high-density memory integration while maintaining compatibility with CMOS technology.
Implementation Method 1
step b) comprises a step of oxidizing the semiconductor layer across its entire thickness
Implementation Method 2
forming by selective epitaxy a semiconductor to fill the openings with first epitaxial portions
Data Source
AI summary
Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.