Vertical BJT and SCR ESD Protection via FinFET Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the number of processing steps and costs when fabricating both field-effect transistors (FETs) and bipolar junction transistors (BJTs) using common processes, especially with the introduction of FinFET devices, while also needing effective protection against electrostatic discharge (ESD) to prevent damage to integrated circuits.
Innovation Solution
The development of an electrostatic discharge (ESD) protection device using a FinFET CMOS process flow, featuring a well region, floating base, and terminal receiving regions with specific doping types, separated by a silicon trench isolation (STI) region, forming vertical bipolar junction transistors or silicon controlled rectifiers to provide robust and efficient ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate BJT and FET fabrication processes are used, then manufacturing precision and device performance are improved, but the number of processing steps and costs increase
Solution Approach 1:
The patent merges BJT and FET fabrication into a single integrated process sequence. The common process steps include: forming isolation regions, depositing mandrel layers, patterning fins, performing selective epitaxial growth for both BJT collector regions and FET channels, and conducting doping operations that serve both device types. This consolidation reduces the total number of processing steps while maintaining the manufacturing precision needed for both BJT and FET performance through carefully controlled shared process parameters.
Solution Approach 2:
The patent creates a universal fabrication process that simultaneously produces both BJT and FET devices. Key process elements serve multiple functions: the same epitaxial growth conditions form both BJT collector regions and FET channels; the same fin patterning process defines structures for both device types; and the same isolation regions serve both BJT and FET devices. This multi-functional approach eliminates redundant process steps while maintaining device-specific performance requirements.
2Ease of manufacture
If common fabrication process is used for BJT and FET, then processing costs are reduced, but process and design challenges increase especially with FinFET devices
Solution Approach 1:
The patent segments the common fabrication process into distinct phases that address different device requirements at appropriate times. The process is divided into: (1) common preparatory steps including isolation region formation and mandrel deposition, (2) fin patterning that creates the foundation for both device types, (3) selective epitaxial growth that forms BJT collector regions in specific areas while defining FET channels in others, and (4) subsequent doping and contact formation. This segmentation allows the common process to handle cost reduction while managing FinFET-specific challenges through targeted process steps.
Solution Approach 2:
The patent performs preliminary actions that prepare the structure for both BJT and FET fabrication before device-specific steps are taken. Key preliminary actions include: forming the fin structures that will serve as the basis for both device types, creating isolation regions that will protect both devices, and depositing mandrel layers that will guide subsequent epitaxial growth. These preliminary steps establish a common foundation that simplifies later device-specific processing and reduces overall complexity.
3Reliability
If traditional lateral BJT devices are used for ESD protection, then ESD protection is provided, but thermal dissipation and trigger voltage performance are limited
Solution Approach 1:
The patent transitions from lateral BJT geometry to vertical BJT geometry for ESD protection. In the vertical configuration, the current flow path is oriented perpendicular to the substrate surface, with the collector region extending vertically above the base region. This dimensional change provides a longer and more direct thermal dissipation path to the substrate, improving heat removal efficiency. The vertical structure also enables a lower trigger voltage by optimizing the electric field distribution along the vertical axis, enhancing ESD protection performance while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces processing steps and costs by integrating ESD protection within existing FinFET processes, offering more robust and efficient protection against ESD, with a lower trigger voltage and deeper discharge path for better thermal dissipation compared to traditional lateral BJT devices.
Implementation Method 1
a second terminal receiving region laterally spaced apart from the first terminal receiving region by a silicon trench isolation (STI) region
Implementation Method 2
A bipolar junction transistor (BJT) requires regions of different doping types, namely n-type and p-type doping types
Data Source
AI summary
An electrostatic discharge (ESD) protection device includes a well region formed from semiconductor material with a first doping type and a floating base formed from semiconductor material with a second doping type. The floating base is disposed vertically above the well region. The ESD also includes a first terminal receiving region formed from semiconductor material with a third doping type. The first terminal receiving region is disposed vertically above the floating base. The ESD further includes a second terminal receiving region. The second terminal receiving region is laterally spaced apart from the first terminal receiving region by silicon trench isolation (STI) region. In some embodiments, the second terminal receiving region is formed from semiconductor material with the third doping type to form a bipolar junction transmitter (BJT) or with a fourth doping type to form a silicon controlled rectifier (SCR).