Vertical Capacitive MEMS Electrodes for CMOS Integration
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Solution Overview
Problem
The integration of microelectromechanical systems (MEMS) devices into CMOS processes at technology nodes below 130 nm poses challenges, including maintaining complexity and sensitivity while minimizing development expenditure and avoiding negative impacts on borophosphosilicate glass polishing, and requiring reduction in additional steps and joint utilization of existing processes.
Innovation Solution
A MEMS device with a movably suspended mass and capacitive structure is manufactured using a CMOS process, where the distance between electrode structures is freely scalable, allowing for miniaturization and improved sensitivity by using a sacrificial layer only to define the gap between electrodes, enabling differential readout of capacitance changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If MEMS devices are integrated into CMOS processes at 130 nm and below, then device integration and miniaturization are improved, but manufacturing complexity and sensitivity are worsened
Solution Approach 1:
The patent transitions from planar capacitor electrodes to vertically stacked three-dimensional electrode structures. The first electrode is formed on the movable mass while the second electrode is formed on the cap structure above it, creating a vertical capacitive sensing arrangement that enables miniaturization without sacrificing sensitivity
Solution Approach 2:
The device is segmented into distinct functional layers: the movable mass containing the first electrode, the intermediate gap region, and the cap structure containing the second electrode. This segmentation allows independent optimization of each component for miniaturization while maintaining overall device sensitivity
2Device complexity
If additional manufacturing steps are reduced, then integration complexity is improved, but manufacturing precision is worsened
Solution Approach 1:
The sacrificial layer is deposited and patterned before the second electrode is formed. This preliminary structuring of the sacrificial layer defines the future electrode gap position, allowing precise gap control to be built into the process early rather than requiring additional alignment steps later
Solution Approach 2:
The sacrificial layer serves as an intermediary structure that temporarily occupies the space between the two electrodes during manufacturing. It acts as a spacer that defines the gap distance, and is subsequently removed to create the final capacitive structure with controlled electrode separation
3Measurement precision
If electrode gap distance is reduced, then sensitivity is improved, but manufacturing precision is worsened
Solution Approach 1:
The patent changes the controlling parameter for gap distance from lithographic dimensions to deposited layer thickness. By controlling the thickness of the sacrificial layer through deposition processes rather than lithographic patterning, sub-100 nanometer gap distances can be achieved with high precision that enables improved sensor sensitivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for CMOS integrable MEMS systems with enhanced sensitivity and reduced manufacturing complexity, maintaining existing integration schemes with minimal additional development expenditure and preserving the stability of the borophosphosilicate glass polishing step.
Implementation Method 1
a capacitive structure comprising a first electrode structure arranged on the movably suspended mass and a second electrode structure arranged at the cap structure such that the first and the second electrode structure form a capacitive structure
Data Source
AI summary
A method for manufacturing a microelectromechanical systems (MEMS) device, includes forming a cavity in a bulk semiconductor substrate; defining a movably suspended mass in the bulk semiconductor substrate by one or more trenches extending from a main surface area of the bulk semiconductor substrate to the cavity; arranging a cap structure on the main surface area of the bulk semiconductor substrate; and forming a capacitive structure. Forming the capacitive structure includes arranging a first electrode structure on the movably suspended mass; and providing a second electrode structure at the cap structure such that the first electrode structure and the second electrode structure are spaced apart in a direction perpendicular to the main surface area of the bulk semiconductor substrate.


