Vertical Capacitor Component Minimizing Terminal Interval
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Solution Overview
Problem
High-frequency capacitor manufacturing faces challenges in achieving low-capacity capacitance due to restrictions in chip design and yield issues when integrating microstrips into substrates for 5G mobile communications, which require high data transmission capacity.
Innovation Solution
A capacitor component design featuring a dielectric with specific dimensions and electrode configurations, where the dielectric is vertically positioned with electrodes larger than themselves, minimizing the interval between input and output terminals to enhance capacitance while maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a microstrip is designed to be installed in a substrate for high-frequency capacitor applications, then the capacitor can be replaced with a microstrip to generate high yield, but the interval between input and output terminals increases, making it difficult to achieve low-capacity capacitance
Solution Approach 1:
The patent transitions from a planar microstrip configuration to a three-dimensional stacked capacitor structure. By stacking multiple capacitor elements vertically, the terminal interval is reduced while maintaining electrical connection, thereby achieving low-capacity capacitance without compromising yield. The stacked architecture allows input and output terminals to be positioned closer together in the vertical dimension rather than extending horizontally.
Solution Approach 2:
The patent employs a nested structure where multiple capacitor elements are stacked within a compact footprint. The insulating layers and electrode patterns are nested vertically, with upper capacitor elements positioned above lower ones. This nesting approach minimizes the horizontal distance between input and output terminals while accommodating multiple capacitance elements, thus achieving low-capacity capacitance with high yield.
2Length of moving object
If the size of electrodes is increased relative to the dielectric to minimize terminal interval, then low-capacity capacitance is achieved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent modifies the geometric parameters of the capacitor structure, specifically making the electrode pattern area larger than the dielectric area. This parameter change allows the electrodes to extend beyond the dielectric boundaries, reducing the terminal interval while providing manufacturing tolerance. The altered parameter relationship (electrode area > dielectric area) simplifies alignment requirements during fabrication.
Solution Approach 2:
The patent divides the capacitor into multiple stacked elements with distinct insulating layers and electrode patterns. Each segment can be manufactured and positioned independently, allowing for easier control of electrode sizes and positions. The segmented structure reduces the cumulative precision requirements compared to a monolithic design, as each layer can be fabricated with standard tolerances.
Data Source
AI summary
A capacitor component includes a dielectric including a first main surface and a second main surface facing each other, and at least one end surface that connects the first main surface and the second main surface, the dielectric being vertically disposed by positioning the at least one end surface on a lower surface of the capacitor component, and a first electrode and a second electrode that are disposed on the first main surface and the second main surface of the dielectric, respectively, wherein a size of each of the first electrode and the second electrode is greater than a size of the dielectric.