Vertical Capacitor-less DRAM Cell Writing Mechanism
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Solution Overview
Problem
Traditional DRAM cells require complex fabrication processes and have limitations in integration and data storage due to their lateral area, and vertical capacitor-less DRAM cells face high power consumption in writing mechanisms.
Innovation Solution
A vertical capacitor-less DRAM cell structure is developed, comprising a source layer, storage layer, active layer, drain layer, address gate, and storage gate, where the storage layer is inserted between the active and source layers, allowing current injection for writing instead of gate-induced drain leakage or impact ionization, reducing the need for high gate dielectric quality and eliminating the overlap requirement between the address gate and drain layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitor-less DRAM cells use GIDL or impact ionization for writing, then data storage capability is achieved, but power consumption increases significantly
Solution Approach 1:
The patent changes the writing mechanism from high-power impact ionization to lower-power direct tunneling by adjusting the energy parameters. The vertical structure enables direct tunneling through the gate dielectric layer, achieving data storage without the high power consumption associated with impact ionization or GIDL mechanisms.
Solution Approach 2:
The patent replaces the mechanical impact ionization process with a quantum mechanical tunneling process. Instead of using high-energy carrier impact to generate electron-hole pairs, the invention utilizes quantum tunneling through the gate dielectric, fundamentally changing the writing mechanism to reduce power consumption.
2Reliability
If vertical capacitor-less DRAM cells use gate overlapping with source/drain for writing, then data storage is achieved, but junction leakage increases
Solution Approach 1:
The patent transitions from a planar geometry to a vertical three-dimensional structure. By stacking the source, storage, and drain layers vertically, the gate can overlap with the storage layer without causing excessive junction leakage, as the vertical configuration separates the gate overlap region from the source-drain junction regions.
Solution Approach 2:
The patent segments the cell structure into distinct vertical layers (source layer, storage layer, drain layer) with different conductivity types. This segmentation allows the gate to selectively overlap with the storage layer while maintaining proper junction isolation, reducing unwanted leakage paths.
3Ease of manufacture
If planar capacitor-less DRAM cells are used, then fabrication is simpler, but lateral area increases limiting integration
Solution Approach 1:
The patent moves from a two-dimensional planar layout to a three-dimensional vertical structure. By stacking functional layers vertically, the cell achieves high integration density with minimal lateral footprint while maintaining compatibility with standard semiconductor fabrication processes that can handle vertical layering.
4Productivity
If high gate dielectric quality is required for vertical capacitor-less DRAM, then writing efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent designs the cell to utilize the inherent properties of the gate dielectric layer as both the tunneling barrier and the isolation medium. The gate dielectric serves multiple functions simultaneously, reducing the need for additional specialized layers or complex manufacturing steps to achieve writing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design lowers the requirement for gate dielectric quality, reduces junction leakage, and decreases power consumption, enabling more efficient data storage with improved integration and longer data holding times.
Implementation Method 1
Capacitor-less DRAM cells store data by floating body effect
Implementation Method 2
the memory cell is written by current injection from the first MOSFET
Data Source
AI summary
A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer.