Vertical Cell String Fabrication for Low Resistance Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in integration due to the high cost and limited capability of forming fine patterns, necessitating the development of a three-dimensional memory cell structure with low resistance characteristics.
Innovation Solution
A method for fabricating a cell string and nonvolatile memory device involving the formation of interlayer dielectric and sacrificial layers on a semiconductor substrate, followed by patterning, metal filling, and annealing to create conductive layers with reduced resistivity, utilizing materials like silicon and aluminum to enhance diffusion and substitution of particles, resulting in a vertical structure with low resistance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional two-dimensional semiconductor memory devices are used, then manufacturing process is simpler, but integration is limited and device price cannot be reduced
Solution Approach 1:
The patent transitions from conventional two-dimensional memory cell arrangement to a three-dimensional vertical cell string structure. The cell string extends vertically from the semiconductor substrate with alternating conductive layers and insulating layers, utilizing the third dimension (height) to increase integration density without requiring finer lateral patterning.
2Productivity
If vertical cell string structure is formed to increase integration, then device price can be reduced, but resistance characteristic deteriorates
Solution Approach 1:
The patent employs annealing treatment to change the physical and electrical parameters of the conductive layers. The annealing process modifies the crystalline structure and reduces resistivity of the conductive materials, thereby improving the resistance characteristic of the vertical cell string structure while maintaining the integrated three-dimensional architecture.
3Productivity
If fine pattern is formed to increase integration of two-dimensional device, then integration increases, but expensive equipment is needed
Solution Approach 1:
The patent forms the memory cell structure vertically along the third dimension rather than expanding laterally in two dimensions. This vertical cell string structure allows integration to increase without requiring progressively finer lateral patterning, thereby avoiding the need for increasingly expensive lithography equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a nonvolatile memory device with low resistance characteristics, enabling increased integration and reduced costs by forming a vertical cell string structure with improved conductivity, thus overcoming the limitations of two-dimensional devices.
Implementation Method 1
annealing the semiconductor pattern having the opening filled with the metal
Implementation Method 2
during annealing a diffusion speed of particles in the sacrificial layer at the interface is higher than that of particles in the metal
Implementation Method 3
heating a predetermined material of the sacrificial layer and the metal in the opening, such that material particle in the sacrificial layer are substituted with metal particles of the metal
Data Source
AI summary
A method for fabricating a cell string includes forming an interlayer dielectric layer, a sacrificial layer, and a semiconductor pattern on a semiconductor substrate, such that the interlayer dielectric layer and the sacrificial layer are formed in a first direction parallel with the semiconductor substrate, and such that the semiconductor pattern is formed in a second direction perpendicular to the semiconductor substrate, forming an opening by patterning the interlayer dielectric layer and the sacrificial layer, filling the opening with a metal, and annealing the semiconductor pattern having the opening filled with the metal.