Vertical Channel Transistor Layout for Low-Resistance Bit Line Contact
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Solution Overview
Problem
As semiconductor devices are scaled down, there is a need for technologies that enhance integration density, operation speed, and production yield, while improving electric and reliability characteristics, particularly in vertical channel transistors.
Innovation Solution
The semiconductor device incorporates a bit line with semiconductor patterns featuring vertical and horizontal portions, word lines, and a gate insulating pattern, where the bottom surfaces of the vertical portions are positioned at a height lower than or equal to the uppermost surface of the bit line, and the word lines are strategically placed to control channel regions effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical channel transistors are used to increase integration density, then integration density and current driving characteristics are improved, but contact resistance and reliability characteristics deteriorate
Solution Approach 1:
The patent transitions from planar channel configuration to vertical channel configuration, changing the dimensional orientation of the transistor channel from 2D to 3D. This vertical extension allows multiple transistors to be stacked above the bit line, significantly increasing integration density while maintaining electrical performance through optimized contact structures at different height levels.
Solution Approach 2:
The patent implements a nested structure where the semiconductor pattern is positioned within or above the bit line structure, and word lines are arranged around the vertical channel portions. This nesting approach allows multiple functional elements to occupy overlapping or adjacent spatial regions, improving integration density without compromising contact reliability through proper structural integration.
2Speed
If vertical channel transistors are used to improve operation speed, then current driving characteristics are improved, but control over channel regions deteriorates
Solution Approach 1:
The patent divides the gate control structure into multiple segmented word lines (first word line and second word line) that are positioned at different locations around the vertical channel portions. This segmentation allows independent control of different channel regions, enabling precise electrical control despite the vertical three-dimensional configuration, thereby maintaining ease of operation while achieving high-speed performance.
Solution Approach 2:
The gate insulating pattern serves as an intermediary layer positioned between the word lines and the semiconductor vertical portions. This intermediary structure enables effective electrical control of the vertical channels while providing necessary insulation and structural support, facilitating proper gate control in the vertical transistor configuration.
3Ease of operation
If word lines are placed on inner side surfaces of vertical portions, then control over channel regions is improved, but device complexity increases
Solution Approach 1:
The vertical semiconductor portions serve multiple functions simultaneously: they act as the channel structure for transistor operation, provide structural support for positioning word lines, and enable three-dimensional integration with the bit line. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity despite the enhanced control capability.
Data Source
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AI summary
A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, first and second word lines adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the first and second vertical portions is located at a height that is lower than or equal to the uppermost surface of the bit line.