Vertical Channel Transistor Layout With Lower Bit Line and Peripheral Gate
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing element sizes while maintaining desired performance, particularly in forming reliable transistors with vertical channel structures.
Innovation Solution
The semiconductor device incorporates a vertical channel transistor with a vertical channel region and a peripheral gate, where the bit line is electrically connected at a lower level, and the peripheral gate is disposed at the same level as the bit line, enhancing integration density and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If element sizes are reduced to increase integration density, then integration density is improved, but transistor performance deteriorates
Solution Approach 1:
The patent transitions from planar transistor structures to vertical channel structures, utilizing the vertical dimension to maintain transistor performance while reducing horizontal footprint. The vertical channel extends in the thickness direction of the semiconductor substrate, enabling higher integration density without sacrificing drive current or switching characteristics.
Solution Approach 2:
The patent implements multiple gating structures (first gate electrode, second gate electrode, and third gate electrode) that are nested or stacked around the vertical channel in different spatial dimensions. This multi-gate configuration provides enhanced gate control over the channel while maintaining a compact footprint, resolving the contradiction between size reduction and performance maintenance.
2Reliability
If vertical channel structures are implemented to maintain performance at smaller sizes, then transistor performance is maintained, but floating body effects increase
Solution Approach 1:
The patent extracts or removes the semiconductor body material from beneath the vertical channel structure, creating a suspended or released channel configuration. This extraction eliminates the floating body effect by removing the bulk semiconductor material that would otherwise generate carrier accumulation and floating body effects, while maintaining the vertical channel's performance benefits.
Solution Approach 2:
The patent introduces a gate insulating film as an intermediary layer between the gate electrode and the vertical channel, and uses this same insulating layer to isolate the channel from the substrate. This intermediary structure provides electrical isolation that prevents floating body effects while maintaining effective gate control over the channel.
3Quantity of substance
If bit line is positioned at lower level to improve integration, then integration density is improved, but electrical connection complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by positioning the bit line at a lower level (different height) relative to the vertical channel structure. This three-dimensional arrangement allows electrical connections to be made through vertical vias or contact holes, enabling high integration density while managing connection complexity through vertical rather than horizontal routing.
Data Source
AI summary
A semiconductor device includes a vertical channel transistor including a vertical channel region extending in a vertical direction and a cell gate electrode facing a first side surface of the vertical channel region. A bit line is electrically connected to the vertical channel transistor at a level that is lower than a level of the vertical channel transistor. A peripheral semiconductor body has at least a portion thereof disposed on a same level as the vertical channel region. Peripheral source/drain regions are disposed in the peripheral semiconductor body and are spaced apart from each other in a horizontal direction. A peripheral channel region is disposed between the peripheral source/drain regions in the peripheral semiconductor body. A peripheral gate is disposed below the peripheral semiconductor body. At least a portion of the peripheral gate is disposed on a same level as at least a portion of the bit line.