Vertical Channel Semiconductor Structure for Floating Body Suppression
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Solution Overview
Problem
Semiconductor devices with vertical channel transistors face challenges in reducing the floating body effect and maintaining target threshold voltage due to impurity diffusion, leading to increased leakage currents.
Innovation Solution
Incorporating an impurity diffusion barrier pattern and a polysilicon pattern doped with impurities, where the impurity diffusion barrier pattern surrounds the polysilicon pattern to prevent impurity diffusion and reduce contact resistance, thereby forming a semiconductor device with improved operating characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity diffusion is allowed in the polysilicon pattern, then contact resistance is reduced, but floating body effect increases and threshold voltage control deteriorates
Solution Approach 1:
The impurity region is segmented into multiple parts: a polysilicon pattern for low contact resistance and an impurity diffusion barrier pattern surrounding it to prevent unwanted diffusion. This segmentation allows each component to fulfill its specific function - the polysilicon provides conductive contact while the barrier prevents floating body effect
Solution Approach 2:
The impurity diffusion barrier pattern acts as an intermediary between the polysilicon pattern and the surrounding semiconductor structures. It mediates the impurity diffusion process by allowing controlled diffusion within the polysilicon region while blocking diffusion into adjacent areas, thus resolving the contradiction between contact resistance and floating body effect
2Productivity
If vertical channel transistors are used for high integration, then device density increases, but impurity diffusion control becomes more difficult
Solution Approach 1:
The impurity diffusion barrier pattern is selectively placed only in critical regions where diffusion control is needed, such as surrounding the polysilicon pattern in the impurity region. This local application maintains manufacturing precision without adding excessive complexity across the entire high-density structure
Solution Approach 2:
The solution addresses diffusion control in the vertical channel transistor by introducing a barrier pattern that operates in the lateral dimension, surrounding the polysilicon pattern horizontally to prevent vertical and lateral diffusion into adjacent channels, thus maintaining precision in high-density vertical structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the floating body effect and maintains the target threshold voltage, resulting in reduced leakage currents and enhanced electrical characteristics of the semiconductor device.
Implementation Method 1
The first impurity region includes an impurity diffusion barrier pattern and a polysilicon pattern doped with impurities. The impurity diffusion barrier pattern prevents diffusion of impurities doped in the polysilicon pattern.
Implementation Method 2
The first impurity region includes an impurity diffusion barrier pattern and a polysilicon pattern doped with impurities.
Data Source
AI summary
A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities.