Vertical Channel Semiconductor Layout for Bit Line Contact Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in increasing integration density and improving operation speed and production yield, particularly in scaling down semiconductor devices with vertical channel transistors, where existing technologies struggle to enhance electric and reliability characteristics effectively.
Innovation Solution
A semiconductor device design featuring a bit line with first and second vertical portions and a horizontal portion, where the word lines are adjacent to the vertical portions, and a gate insulating pattern is placed between the vertical portions and the word lines, with the bottom surfaces of the vertical portions located at a height lower than or equal to the uppermost surface of the bit line, enhancing control over channel regions and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical channel transistors are used to increase integration density, then integration density improves, but contact resistance between bit line and semiconductor pattern increases
Solution Approach 1:
The patent transitions from planar contact geometry to three-dimensional contact geometry by forming vertical portions that extend downward from the semiconductor pattern. This dimensional change allows the bit line to contact the semiconductor pattern at multiple levels (top surface and bottom surface of vertical portions), increasing contact area and reducing contact resistance while maintaining high integration density through vertical channel architecture.
2Speed
If vertical channel transistors are used to improve operation speed, then operation speed improves, but control over channel regions becomes more difficult
Solution Approach 1:
The patent segments the gate structure into multiple independent word lines (first word line and second word line) that can independently control different channel regions. The first word line controls the first channel region formed between the bit line and first word line, while the second word line controls the second channel region formed between the bit line and second word line. This segmentation enables precise control over vertical channel regions, facilitating improved operation speed through independent gate control.
Data Source
AI summary
A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion to be adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the horizontal portion may be located at a height that is lower than or equal to the uppermost surface of the bit line.