Vertical Semiconductor Channel Layout for DRAM Cell Scaling
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Solution Overview
Problem
DRAM manufacturers face challenges in shrinking memory cell area due to shrinking word line spacing, necessitating precise control over channel length in semiconductor devices.
Innovation Solution
A semiconductor device design with doped regions of opposing conductive types, aligned with word lines, allowing for precise control of channel length and enabling formation of doped regions without considering thermal budgets of other wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If word line spacing is shrunk to reduce memory cell area, then memory cell density is improved, but control over channel length becomes less precise
Solution Approach 1:
The patent transitions from planar channel formation to vertical channel formation by stacking semiconductor layers. The channel length is now controlled in the vertical dimension through layer thickness and stacking configuration, allowing precise channel length control independent of the shrunk word line spacing in the horizontal plane. This dimensional change resolves the contradiction by decoupling channel length control from word line spacing constraints.
Solution Approach 2:
The patent divides the semiconductor structure into multiple stacked layers with alternating doped regions (n-type and p-type) forming discrete vertical channels. Each channel segment is precisely defined by the stacking sequence and thickness of individual layers, enabling independent control of channel length through layer design rather than being constrained by word line spacing.
2Ease of manufacture
If doped regions are formed using conventional methods, then manufacturing process is simple, but thermal budget constraints limit feature formation flexibility
Solution Approach 1:
The patent forms doped regions and semiconductor layers in a predetermined stacking sequence during the initial fabrication stages, before subsequent high-temperature processing steps. This preliminary formation of doped regions with alternating conductive types allows later thermal processing to proceed without being constrained by thermal budget limitations, as the critical doped structures are already in place.
Solution Approach 2:
The patent segments the fabrication process into distinct stages where doped regions are formed separately and stacked in a specific sequence. This segmentation allows each doped region to be formed and positioned independently, providing flexibility in thermal budget management for subsequent processing steps without compromising the integrity of previously formed doped structures.
Data Source
AI summary
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, a semiconductor layer, and a word line. The bit line is disposed over the substrate. The semiconductor layer is disposed over the bit line. The word line abuts the semiconductor layer. The word line has a lower surface facing the substrate and an upper surface opposite to the lower surface. The semiconductor layer includes a first doped region with a first conductive type, a second doped region with a second conductive type opposite to the first conductive type. The first doped region is disposed between the second doped region and the bit line. The first boundary between the first doped region and the second doped region is substantially aligned with the lower surface of the word line.