Vertical Channel Memory Cell Structure for Higher Integration Density
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Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited due to the need for expensive apparatuses to miniaturize patterns, hindering cost-effective high performance.
Innovation Solution
A semiconductor device with vertical channel transistors (VCTs) incorporating active and peri-active patterns, bit lines, and peri-gate structures, which enhance integration density and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor memory device structure is used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by forming vertical channels that extend in the depth direction (z-axis). The active pattern rises vertically from the substrate, with gate structures wrapping around the channel in multiple directions, thereby utilizing the third dimension to increase integration density without complicating the fundamental manufacturing approach
2Quantity of substance
If pattern miniaturization is pursued to increase integration density, then integration density improves, but expensive apparatuses are required
Solution Approach 1:
Instead of continuing to miniaturize patterns in the planar direction which requires expensive lithography equipment, the patent forms vertical channels that extend in the depth direction. This allows integration density to increase by utilizing the vertical dimension rather than continuously shrinking horizontal features, thereby avoiding the need for increasingly expensive lithography apparatuses
Solution Approach 2:
The patent changes the structural parameter from horizontal planar dimensions to vertical depth dimensions. By forming channels that extend vertically and gates that wrap around in three dimensions, the design shifts the scaling parameter from lateral feature size to vertical channel length and gate thickness, enabling density improvement without relying on further planar miniaturization
3Quantity of substance
If vertical channel transistor structure is implemented, then integration density increases, but device complexity increases
Solution Approach 1:
The vertical channel structure is segmented into distinct functional regions: the active pattern forming the channel, the gate structure wrapping around the channel, the bit line extending in the first direction, the data storage pattern, and the peri-active pattern with its own gate structure. This segmentation allows each component to be formed and controlled independently, managing the complexity of the three-dimensional structure
4Quantity of substance
If unit memory cell area is reduced to increase integration density, then integration density improves, but electrical characteristics may deteriorate
Solution Approach 1:
The patent maintains good electrical characteristics by forming vertical channels that extend in the depth direction, allowing the channel length to be determined by vertical depth rather than horizontal width. This enables smaller planar footprints while maintaining adequate channel length for proper electrical performance, and the multi-directional gate structures provide effective electrostatic control of the channel
Data Source
AI summary
There is provided a semiconductor device having improved integration density and electrical characteristics. The semiconductor device includes a first peri-gate structure on a substrate, an active pattern that is spaced apart from the substrate in a first direction and includes a first surface and a second surface opposite to each other in the first direction, a peri-active pattern that is spaced apart from the substrate in the first direction and includes a first surface and a second surface opposite to each other in the first direction, a second peri-gate structure on the first surface of the peri-active pattern, a bit line that is electrically connected to the first surface of the active pattern and extends in a second direction intersecting the first direction, and a data storage pattern electrically connected to the second surface of the active pattern.