3D Vertical Channel Memory Structure for Higher Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-dimensional semiconductor devices face integration limitations due to the high cost of fine pattern forming technology, limiting their ability to increase storage capacity and reduce costs.
Innovation Solution
A three-dimensional semiconductor device with a vertical channel structure is fabricated by alternately stacking interlayer insulating layers and sacrificial layers, forming vertical channel holes, and creating active layers with horizontal and vertical portions, allowing for increased integration and improved electrical and reliability characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited due to area constraints and high cost of fine pattern forming technology
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertical channel structures. The vertical channels extend in the depth direction (z-axis) through alternating sacrificial and interlayer insulating layers, enabling integration scaling without requiring finer lateral patterning. This dimensional transition allows continued productivity improvement while maintaining manufacturing feasibility.
2Productivity
If fine pattern forming technology is advanced to increase integration, then storage capacity increases, but process equipment cost increases extremely
Solution Approach 1:
Instead of increasing lateral pattern fineness, the patent uses vertical stacking of alternating sacrificial and interlayer insulating layers to create three-dimensional channel structures. This approach achieves higher storage capacity through increased vertical integration rather than lateral miniaturization, avoiding the need for extremely expensive fine pattern forming equipment.
Solution Approach 2:
The patent segments the device structure into alternating sacrificial layers and interlayer insulating layers stacked vertically. This segmentation creates discrete, manageable layers that can be formed using standard deposition and etching processes, avoiding the need for advanced fine pattern forming technology while achieving high integration through vertical stacking.
3Productivity
If vertical channel structure is formed, then integration and storage capacity increase, but device complexity increases
Solution Approach 1:
The vertical channel structure is achieved through segmentation into alternating sacrificial layers and interlayer insulating layers. Each layer serves a specific function and can be formed using standard processes, making the complex three-dimensional structure manufacturable through repeated application of simple, well-established fabrication steps rather than requiring complex single-step processes.
Data Source
AI summary
A method of fabricating a semiconductor device may include forming a lower mold structure on a substrate, forming a first mold structure on the lower mold structure, the first mold structure including first interlayer insulating layers and first sacrificial layers, which are alternately stacked in a vertical direction, forming first vertical channel holes to penetrate the first mold structure, the lower mold structure, and a portion of the substrate, and forming an active layer to cover a top surface of the first mold structure and extend to an upper side surface of each of the first vertical channel holes. The active layer may include a horizontal portion covering the top surface of the first mold structure and a vertical portion covering the upper side surface of each of the first vertical channel holes, and the active layer may include a metallic material.