Vertical Channel Semiconductor Fabrication for Contact Resistance Control
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Solution Overview
Problem
The challenge in fabricating semiconductor devices with vertical channels is the increased difficulty in controlling contact resistance, particularly when the linewidth falls below 20 nm, leading to instability and improper functioning due to short channel effects.
Innovation Solution
A method involving the sequential formation of a diffusion barrier film, semiconductor film, silicide film, and conductive film on a semiconductor substrate, followed by patterning to create a pillar structure and gate electrode, which helps in forming a stable contact resistance by preventing impurity diffusion and ensuring proper pillar formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical channel semiconductor devices are scaled down to improve transistor density and performance, then device miniaturization is achieved, but contact resistance control becomes difficult and fabrication difficulty increases
Solution Approach 1:
The patent segments the contact structure into multiple distinct layers: a lower electrode, a barrier layer, and a silicide layer. This segmentation allows each layer to perform its specific function independently, with the barrier layer specifically designed to control contact resistance at the interface between the lower electrode and the vertical channel, thereby solving the contact resistance control problem while maintaining high transistor density
Solution Approach 2:
The patent introduces a barrier layer as an intermediary between the lower electrode and the vertical channel. This barrier layer acts as a mediator that controls and stabilizes the contact resistance at the interface, preventing direct contact between the electrode and channel materials. This intermediary structure enables reliable electrical contact even at scaled dimensions below 20 nm linewidth
2Speed
If channel length is reduced below the limit to improve device performance, then transistor speed increases, but short channel effects occur that limit proper functioning
Solution Approach 1:
The patent transitions from a planar channel structure to a vertical channel structure that extends in the depth dimension. This dimensional change allows the channel to achieve sufficient effective length for controlling short channel effects while maintaining a small footprint on the surface, enabling both high speed and reliability in scaled devices
Solution Approach 2:
The patent employs composite material structures including the barrier layer composed of specific materials (such as titanium nitride or tungsten silicide) combined with the vertical channel materials. This composite structure provides both the electrical conductivity needed for high speed operation and the interface control needed to suppress short channel effects, achieving both improved speed and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the control of contact resistance and enhances the stability of semiconductor devices by preventing impurity diffusion and ensuring proper pillar formation, thus overcoming the limitations of short channel effects and fabrication difficulties.
Implementation Method 1
forming a diffusion barrier film on a semiconductor substrate
Implementation Method 2
forming a silicide film on the semiconductor film
Data Source
AI summary
A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a semiconductor film on the semiconductor substrate in which the diffusion barrier film is formed, forming a silicide film on the semiconductor film, forming a conductive film on the silicide film, forming an upper portion of a pillar structure in a first region of the semiconductor substrate by patterning the conductive film, the silicide film, and the semiconductor film, forming a lower portion of the pillar structure by patterning the diffusion barrier film and the semiconductor substrate in the first region, and forming a gate electrode on an outer side of a patterned semiconductor substrate.