Vertical Channel TFT for High ON Current Without Aperture Loss
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Solution Overview
Problem
In high-speed and high-density liquid crystal displays, the ON current of thin-film transistors (TFTs) needs to be improved to charge pixels quickly, but increasing the width of the channel region reduces the aperture ratio and increases parasitic capacitance, while reducing the length is limited by exposure facilities.
Innovation Solution
A TFT substrate with shorter channel lengths is manufactured by forming a semiconductor pattern on an insulating substrate, with source and drain electrodes on top and bottom surfaces, a gate electrode alongside with a gate insulating film, and a pixel electrode connected to the drain electrode, allowing for controlled channel region dimensions despite exposure limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the width of the channel region is increased to improve ON current, then the ON current increases, but the aperture ratio decreases and parasitic capacitance increases
Solution Approach 1:
The patent transitions from controlling channel width (2D plane dimension) to controlling channel thickness (3D vertical dimension). By forming the semiconductor pattern as a thin film with controlled thickness and using a gate electrode that overlaps the channel region, the invention enables independent control of channel length through vertical stacking rather than horizontal expansion, thus improving ON current without sacrificing aperture ratio.
2Power
If the width of the channel region is increased to improve ON current, then the ON current increases, but parasitic capacitance increases
Solution Approach 1:
The invention moves the control parameter for channel length from the lateral dimension to the vertical dimension through thin-film semiconductor structures and overlapping gate electrodes. This dimensional transition allows achieving higher ON current through increased channel width while keeping parasitic capacitance low by maintaining minimal overlap areas and using thin-film configurations that reduce capacitive coupling.
3Power
If the length of the channel region is reduced to improve ON current, then the channel length decreases, but exposure facility limitations prevent further reduction
Solution Approach 1:
The patent circumvents exposure facility limitations by forming the semiconductor channel as a thin film structure where the effective channel length is controlled by the gate electrode overlap distance rather than by lateral patterning. This allows achieving shorter effective channel lengths (e.g., 50-100 micrometers) that are difficult to achieve with conventional exposure methods, thereby improving ON current without being constrained by exposure tool capabilities.
Data Source
AI summary
Provided is a thin-film transistor (TFT) substrate. The TFT substrate includes: an insulating substrate; a semiconductor pattern which is formed on the insulating substrate, the semiconductor pattern having a top surface and a bottom surface; a source electrode and a drain electrode which are disposed on the top and bottom surfaces of the semiconductor pattern, respectively; a gate electrode which is disposed alongside the semiconductor pattern with a gate insulating film interposed therebetween; a data line which is connected to the source electrode and extends in a first direction; a gate line which is connected to the gate electrode and extends in a second direction; and a pixel electrode which is connected to the drain electrode and is formed in a pixel region.