Vertical Channel Transistor for Phase Change Memory Density
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Solution Overview
Problem
Existing high-density memory devices face challenges in achieving both vertically and horizontally oriented field effect transistors on a single substrate due to manufacturing complexity and etching damage issues, which affect the density and performance of phase change memory cells.
Innovation Solution
The integration of both vertically and horizontally oriented field effect transistors on a single substrate, with a manufacturing method that includes forming a substrate with specific dielectric layers and terminals, and using a silicide process to create conductive caps and word lines, allowing for a small cross-sectional area while maintaining sufficient current for phase change operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional horizontally oriented field effect transistors are used to reduce cross-sectional area, then device density is improved, but current drive capability deteriorates
Solution Approach 1:
The patent transitions from traditional horizontal field effect transistors to vertically oriented field effect transistors, changing the spatial orientation from two-dimensional planar structure to three-dimensional vertical structure. This dimensional change allows the channel to extend vertically through multiple dielectric layers, achieving high current drive capability while maintaining small cross-sectional footprint for high-density memory arrays.
2Manufacturing precision
If etching is used to reduce phase change element size, then current density is improved, but material damage increases
Solution Approach 1:
The patent extracts the phase change material from the etching process entirely. Instead of forming phase change elements through etching, the invention uses a blanket deposited phase change material layer that is subsequently patterned by lifting the overlying dielectric and conductor layers. This extraction eliminates etching damage to the phase change material while maintaining precise size control through the lifting process.
Solution Approach 2:
The patent introduces dielectric and conductor layers as intermediary elements between the phase change material and the patterning process. These intermediary layers are patterned and lifted to define the phase change element geometry, protecting the phase change material from direct exposure to etchants while enabling precise size control through the lifting mechanism.
3Adaptability or versatility
If vertically oriented field effect transistors are integrated with horizontally oriented transistors on the same substrate, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the substrate into distinct first and second regions, with the first region containing horizontally oriented field effect transistors and the second region containing vertically oriented field effect transistors. This spatial segmentation allows each region to be optimized for its specific transistor orientation while sharing common manufacturing processes for substrate preparation, dielectric layer formation, and phase change material deposition, thereby reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density memory devices with reduced manufacturing complexity and etching damage, providing sufficient current for phase change operations while maintaining high memory cell density and compatibility with CMOS periphery circuitry.
Implementation Method 1
using a silicide process to create conductive caps and word lines
Implementation Method 2
Phase change memory cell having vertical channel access transistor
Implementation Method 3
The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state
Implementation Method 4
a short high current density pulse to melt or breakdown the crystalline structure
Data Source
AI summary
A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.