Vertical Dielet SiP Thermal Management Without Through Silicon Vias
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Solution Overview
Problem
Conventional system-in-packages (SiPs) face challenges with thermal conductivity and interconnection issues due to the parallel orientation of dies, which limits heat dissipation and increases die size, as vertical through silicon vias are difficult to manufacture and consume valuable die area.
Innovation Solution
The SiP configuration includes a host die with vertically oriented dielets and thermal spreader materials, eliminating the need for through silicon vias by maximizing contact between the host die and dielets with thermal spreaders for efficient heat dissipation and interconnection using die-level interconnect structures such as thermocompression bonded conductive materials or 3D additive printing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional parallel stacking of dies is used, then manufacturing is simpler, but thermal conductivity deteriorates due to insufficient heat dissipation paths
Solution Approach 1:
The patent transitions from conventional parallel (2D) stacking to vertical (3D) stacking of dies, where dies are oriented perpendicular to the substrate. This dimensional change creates additional thermal dissipation paths through the vertical orientation, improving thermal conductivity while maintaining manufacturing feasibility through standardized bonding processes.
2Ease of manufacture
If vertical through silicon vias are used for interconnection, then interconnection is achieved, but die area is reduced due to via consumption and manufacturing difficulty
Solution Approach 1:
The patent extracts the interconnection function from the die substrate itself (removing the need for through silicon vias) and implements it through vertical die stacking with bonding interfaces at the periphery. This separates the interconnection path from the active logic area, allowing full utilization of die area for logic functions while achieving robust interconnection through the vertical stacking architecture.
3Temperature
If vertical die stacking is implemented, then thermal conductivity improves, but device complexity increases due to new interconnection methods
Solution Approach 1:
The patent creates a universal vertical stacking architecture that simultaneously achieves multiple functions: thermal dissipation through vertical orientation, interconnection through peripheral bonding interfaces, and logic function implementation on full die area. This multi-functional approach reduces overall system complexity by consolidating interconnection and thermal management into the structural arrangement rather than requiring separate complex subsystems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances thermal conductivity and package rigidity, allowing for effective heat dissipation without the need for through silicon vias, thereby addressing thermal and interconnection challenges in SiPs.
Implementation Method 1
The bulk sides of the dielets, as well as the uncovered portions of the logic side of the host die, are surrounded by thermal spreader materials to allow efficient heat dissipation through the dielets and host die
Implementation Method 2
The die-level interconnect structures include thermocompression bonded conductive materials
Data Source
AI summary
A system-in-package (SiP) incorporating] is disclosed. In embodiments, the host die defines a substantially horizontal plane (e.g., via its active side). One or more vertical dielets are attached to, and interconnected with, the active side of the host die in a substantially vertical configuration (e.g., perpendicular to the host die). Due to the perpendicular orientation of the dielets, the SiP incorporates thermal spreaders in thermal contact with the active side of the host die as well as the inactive sides of the dielets, allowing for thermal dissipation from the host dies and dielets without the need for through silicon vias.