Vertical DMOS Trench Gate Reduces Chip Area
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Solution Overview
Problem
As the required breakdown voltage increases, the length of lateral drain-extended metal oxide semiconductor field effect transistors (LDMOS) lengthens, leading to an increase in chip size, which poses a challenge in integrating power devices with analog ICs on a single chip effectively.
Innovation Solution
The semiconductor device incorporates a vertical drain-extended metal oxide semiconductor field effect transistor (VDMOS) configuration with a trench gate structure and deep trench isolation (DTI) to reduce the horizontal size of the DMOS element, allowing for the integration of power devices and analog ICs on a single chip while maintaining adequate breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDMOS element length is increased to achieve higher breakdown voltage, then breakdown voltage is improved, but chip size increases
Solution Approach 1:
The patent transitions from a lateral drain structure (LDMOS) to a vertical drain structure (VDMOS), changing the current flow direction from horizontal to vertical. This dimensional change allows the breakdown voltage to be determined by vertical drift region thickness rather than horizontal element length, thereby reducing chip area while maintaining high breakdown voltage capability
Solution Approach 2:
The patent inverts the traditional LDMOS architecture by placing the drain at the top surface and source at the bottom (or vice versa), with the current flowing vertically through the semiconductor layers. This inverted structure achieves the same electrical function with a compact footprint, resolving the contradiction between breakdown voltage and chip size
2Area of stationary object
If deep trench isolation is implemented to reduce horizontal size, then chip area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor structure into distinct vertical segments separated by deep trench isolation regions. The trenches partition the device into isolated vertical columns, each functioning independently. This segmentation enables compact horizontal spacing while maintaining electrical isolation, reducing overall chip area without proportionally increasing manufacturing complexity
Solution Approach 2:
The deep trench isolation acts as an intermediary structure that physically and electrically separates adjacent active regions. By introducing this intermediate isolation layer, the patent enables tighter horizontal spacing between devices while maintaining adequate isolation, effectively reducing chip area with manageable manufacturing overhead
Data Source
AI summary
According to one embodiment, the fifth semiconductor region contacts the first semiconductor region. The metal region is provided on the fifth semiconductor region. The first insulating film extends in a thickness direction of the semiconductor layer. The first insulating film is adjacent to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, and the first semiconductor region. The second insulating film extends in the thickness direction of the semiconductor layer. The second insulating film is provided between the fourth semiconductor region and the first conductive unit, between the third semiconductor region and the first conductive unit, and between the second semiconductor region and the first conductive unit.